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Esprit Project 22495 - VAHMOS 2000
The vertical advanced heterojunction MOS transistor as a building block for CMOS from the year 2000 on

Keywords: SiGe/ Si, MBE , CVD, CMOS, vertical MOS transistor, Drain Induced Barrier Lowering (DIBL)

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At the international workshop on 'Future Information Processing Technologies", (Porvoo, September 1995), attended by major Microelectronics companies and research sites, one of the conclusions was that the vertical MOS transistor is the device concept of the future. In establishing its potential advantages and assessing its performance with respect to today's classical scenarios, a technology which provides denser and faster structures, but uses the same generation of production equipment will be initiated.

Taking the present transfer activities of the SiGeHBT to production lines into consideration, the SiGe technology will be implemented in most of the Si lines, which will facilitate a seamless and low cost transfer of the new SiGe MOS into production.

Present projections based on for the operation of a 20 nm channel length vertical device at room temperature result in an on-current of 20000 µA/µm, an off-state current less than 1 pA/ µm2 , a transconductance of more than 3500 mS/mm, a VT of less than 0.3V at Vdd= 1V and an intrinsic carrier transit time of less than 1 ps. Given this outstanding performance compared to conventional CMOS one can foresee a realistic chance to win huge market segments in mainstream CMOS .

It is the intention of the project not really to reach from a first shot these projected results which apply to "ideal" structures but to demonstrate the feasibility of both n-channel and p-channel vertical heterojunction field effect transistors proving far superior characteristics (drive current, off-state current, speed, transconductance...) made by a cost effective technology. In addition, a production friendly thin layer sequence will be allowed by a novel buffer layer concept. The validity of this concept will be demonstrated by the growth of a complete vertical stack as a demonstrator for CMOS feasibility.

In scaling down the classical planar MOS device towards deep submicron dimensions the most important technological limit encountered is the definition of the channel length by practical lithographic techniques. From a physical point of view the short channel effect which translates into Drain Induced Barrier Lowering (DIBL) and as such into threshold voltage roll off and off-state leakage current is the most important limitation.

In this project a new vertical heteroMOS structure is proposed which solves the above problem because of the following characteristics:

In addition to solving the above limitations by the special architecture the heterojunction is made by a SiGe/ Si (pMOS) or SiGe/Ge (nMOS) combination. These materials are fortunately compatible with Si technology, allowing later for an easy integration into production.

Both pMOS and nMOS devices will be fabricated using 2 different approaches for the epitaxial growth, namely MBE and CVD.

The work in this project is organised into 5 workpackages:


Contact Point
Prof. Dr. Ir. Kristin De Meyer
Interuniversity Microelectronics Centre (IMEC)
Advanced Semiconductor Processing (ASP)
Kapeldreef 75
B - 3001 Leuven


e-mail: (E-mail removed)

Start date: 1 January 97
Duration: 36 months


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