Project home page: http://www.intec.rug.ac.be/oiic/
In this project, we want to find solutions to the difficulties of electronic interconnects to handle high throughput data transfer within and between silicon VLSI chips. This fundamental problem arises from the ever increasing IC complexity, speed and interconnection requirements. Several European research projects (e.g. OLIVES, HOLICS and SPIBOC) have proposed optical solutions to this interconnect bottleneck at a higher level of interconnect hierarchy (inter-cabinet and backplane interconnects). It is the main goal of this project to establish key technologies and define relevant processing architectures allowing introduction of area (as opposed to edge) optical interconnections for intra- and inter-MCM data exchange.
The project will advance the current state-of-the-art in opto-electronic components (LEDs, VCSELs and PDs) as well as in hybridisation onto CMOS (flip chip mounting of dense opto-electronic component arrays) and packaging. Optical pathways (guided wave POF-based a, free space PMMA based optical pathways and image fiber bundles), compatible with CMOS area optical interconnect, are a key focuse of this project. Demonstrators will be constructed at the technology level, the link and the system level.
The system demonstrator (schematically shown in figure 1) will connecting two packaged, programmable chips, through area optical interconnect (two 4x8 uni-directional links per chip). These chips fill harbour a programmable FPGA-architecture. Aggregate bit rate (I/O per chip) will exceed 10 Gb/s.
Technoly demonstrators include CMOS compatible 1 Gb/s per channel optical links, manufacturable 8x8 POF connectors and ferrules, substrate removal process development for mounting devices emitting/detecting at 850 nm, high density (100 channels/mm2) optical pathways based on free space PMMA-parts and image fibre bundles and integrated CMOS detectors operational upto 500 Mb/s.
Based on these novel technologies, two link demonstrators will be constructed : a highly parallel link running at moderate bitrates (channel density 100 channels/mm2, bitrate 300 Mb/s per channel) and a 2x8 high speed link (pitch 250 m m, bitrate 1 Gb/s per channel).
Prof. Roel Baets
Interuniversitair Micro-Elektronica Centrum (IMEC)
e-mail: (E-mail removed)
1 September 96
Duration: 48 months
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