Project home page: http://www.phy.hw.ac.uk/resrev/SPOEC/
As feature sizes on silicon IC's become smaller and the performance of individual chips becomes more powerful, so the problem of providing a proportional increase in external input/output capacity becomes harder. Physical limits on the numbers, and bandwidth of, electrical pin connections create a substantial bottleneck. This project aims to develop and exploit smart-pixel techniques, which provide three-dimensional optical interconnects based on multiple free-space connections distributed across the full area of the chip in array format.
The objectives of the project and the approaches to be taken can be summarised as follows:
The proposed 3-D free-space approach is particularly attractive as, by permitting the construction of high-throughput reconfigurable interconnects (such as the crossbar switch), it could rapidly open up the construction of powerful information processing machines based on highly interconnected processor and memory blocks. This would include massively parallel systems and advanced shared/distributed memory machines. One could therefore anticipate significant impact on all those applications currently looking to exploit highly-parallel computing systems - an increasing domain, encompassing tasks such as engineering simulations, computational science applications, real-time image processing and game/entertainment systems. Distributed sensing/control systems in which large amounts of data need to be communicated from node to node with minimal delay will be another important application.
The project will explore the long-term potential of this approach, which offers the prospect of creating wide-band links to advanced Si-IC's with no limitation on connection distance and with aggregate bandwidths in excess of 10 Tbit/s.
Prof. A. C. Walker
Department of Physics
UK - Edinburgh - EH14 4AS
e-mail: (E-mail removed)
1 September 96
Duration: 36 months
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