Our long term objectives are :
The results of the project will provide information on the feasibility of using single electron charging effects as the basis for a future memory technology. The research will also advance nanofabrication technology and nano-scale processing technology for semiconductor devices.The architecture will be developed while taking into account the strengths and weaknesses of single electron devices. New concepts will need to be realised for inter-connected devices and circuits, and methods for low power coupling between devices as well as between SETS and CMOS will be researched.
The basic SETS will require a fabrication strategy for metallic and semiconductor based devices. These will take into account the need to develop strategies which will eventually lead to practical production methods. Low power consumption in the circuits will be of prime importance, but attempts will also be made to raise the operating temperature of the SETS to levels which are significantly higher than 4.2K, and possibly room temperature. Towards the conclusion of the project, primitive memory circuits based on SETs will be realised and their performance will be compared to CMOS circuits. Throughout the project experimental work will be strongly supported by the simulation of device structures and the fabrication will be optimised on the basis of the guidance received. Simulation will also support electrical properties of SETS and memory devices. The simulation will be based on an in-depth understanding of the physics underlying the Coulomb blockade effect and is likely to be a vital requirement.
Pushing the nanofabrication methods to the sub-50nm level with a good control of regularity and created defects, and explore the feasibility of mass nanofabrication will benefit to any field relevant to ultra-high resolution nanofabrication: single electron electronics, photonics, nanomagnetism...
The benefits of making SET memories are the reduced size of the individual memory cells, the reduced power consumption and the possibility to integrate them with Si logic. A memory cell has only two requirements : 1) that its state can be changed to represent a <<1 >> or <<0>>, and 2) that its state can be sensed. With SET memories this could be accomplished with the movement of a single electron. For today's DRAMs this is done by charging and discharging a capacitor. With SETs a chip of one terabit capacity would not exceed a few cm2.
In very special applications, single-electron memory could be used in commercial products within 10 years. More general applications could be expected by the year 2015 as predicted by the trend curves of semiconductor memory technology. This project offers a real prospect for commercial exploitation in 10 to 15 years if the research is successfully carried out.
Dr. Huguette Launois
Laboratoire de Microstructures et de Microélectronique (L2M)Centre National de Recherche Scientifique (CNRS)
196 Avenue Henri Ravera
F- 92225 Bagneux Cedex
e-mail: (E-mail removed)
1 January 97
Duration: 36 months
Welcome to the new
Information Society Technologies Programme (IST)
Our new activities in the IST Programme:
Future & Emerging Technologies
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