It is expected that CMOS will begin to reach its technological or financial limits in the first decade of the next century. Its deficiencies will first appear as bottlenecks where there is no alternative to high speed. This project is aimed at developing the technology to fill these bottlenecks. Single Flux Quantum (SFQ) has strengths complementary to CMOS : it is capable of extremely high speed at very low power dissipation. Typical speed power products for SFQ are less than 10 -17 J, while state of the art CMOS might attain 10 -14 to 10 -13 J. CMOS will undoubtedly continue to improve, but probably only has one additional order of magnitude of improvement left. Against these performance advantages must be set the burden of cooling, which will limit early use to critical components that leverage overall system performance.
The architecture which allows the very high speeds is particularly well suited to data local operations such as are common in communications and signal processing. It is often predicted that the first major bottleneck in the capabilities of conventional electronics will be in packet switching networks; this function would be admirably suited to implementation in SFQ. It is worth pointing out that local processing is the consequence of the high clock speed, not the technology; it is highlighted for SFQ simply because it is the first logic family to operate so fast.
Before HTS-SFQ can become a commercial proposition, the fabrication technology must be developed and the design methods established. The aim of this project is to improve the technology to the point where a fairly complex demonstrator circuit can be made. This demonstration will be a major step in showing the industrial potential of the technology.
To establish understanding of the design, fabrication, and applications potential of High Temperature Superconducting (HTS) Single Flux Quantum (SFQ) logic.
The consortium proposes to: (1) Establish a common design base for these circuits. (2) Develop and demonstrate a suitable technology. (3) Develop techniques for testing and diagnosing SFQ circuits. (4) Demonstrate a complete SFQ circuit function, including interfaces to conventional CMOS technology, of up to an order of magnitude greater complexity than previous HTS circuits. (5) Recommend directions for future development and interact with other novel logic programmes through the roadmap group to provide a balanced European perspective of their potential.
To achieve the above objectives four partners propose to join forces. The project will be led by the University of Twente (The Netherlands). The other partners are Chalmers University of Technology (Sweden), the Defence Research Agency (UK) and Thomson/CSF Laboratoire Central de Recherches (France). These groups are amongst the leaders in Europe in HTS circuit technology and have state of the art capabilities. Their technologies are complementary to maximise the chances of success. Only the best of these technologies will be selected to make the demonstrator. The project is part of the Nano-Scale Integrated Circuits
Prof. Dr. Horst Rogalla
University of Twente
Applied Physics, Low Temperature Division
Drienerlolaan 5 (PO Box 217)
NL - 7500 AE Enschede
e-mail: (E-mail removed)
1 January 97
Duration: 48 months
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