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Esprit Project 23544 - HSLA
Open LTR €“ 1 st phase
( 2 nd phase see project 33544 )
A High Speed Logarithmic Arithmetic unit

Keywords: Logarithmic Number System arithmetic (LNS), digital signal processing


There is a world-wide demand for accurate, high-performance arithmetic devices. These find application in two primary areas : general-purpose computing (e.g. Intel Pentium) and digital signal processing (e.g. Texas Instruments 320C40).

Currently the universal technique for performing real arithmetic is floating-point. Rates of performance for devices using it are about 30 - 40 ns latency for 32-bit add. subtract and multiply. Division takes considerably longer, and all four operations are subject to a maximum half-bit rounding error.

There is, of course, a constant demand for higher speed and accuracy in almost any application area. Examples include the requirement or higher data-rates in FFT. Filtering and general-purpose arithmetic, evident throughout most areas of digital communications. image processing, radar and sonar, and desktop computing. Large specialised application areas are rapidly emerging, e.g. in multimedia and digital television. It is the objective of this project to increase the speed and accuracy at which real arithmetic can be performed by using the Logarithmic Number System (LNS), instead of floating-point.

In the LNS a real value is represented as its fixed-point logarithm. The primary advantage of the LNS is therefore that multiplication and division involve only a fixed-point addition or subtraction, and are thus performed in minimal time and with no rounding error. LNS addition and subtraction, however, have hitherto been considerably slower, less accurate or less precise than their floating-point counterparts, and have therefore nullified the advantages to be gained by using this technique. It is the objective of this project to develop LNS addition and subtraction techniques which are approximately as precise, fast and accurate as floating-point, and which in conjunction with LNS multiplication and division would therefore yield a substantial improvement in average speed and accuracy over floating-point.

A research programme is proposed which has the following aims in its 1st phase.

This work during the 1st phase will be aimed at finalising the arithmetic algorithms and proving their superiority over floating-point. Theoretical refinements will be made to the algorithms in order to achieve the targets for speed and accuracy. A software simulation will be made available with which the accuracy of the system can be evaluated against that of floating-point, and proven over a range of larger-scale applications. A software library of DSP applications will be built. A detailed ALU cell design will be done, and from this it will be shown that the device will meet the target speed, and that it can economically be fabricated.

Once the feasibility of the approach has been demonstrated and the objectives of the 1st phase have been achieved the project will enter into a second phase with the following aims:

Contact Point
Dr John Nicholas Coleman
University of Newcastle upon Tyne
Electrical and Electronic Engineering
Merz Court
UK - Newcastle upon Tyne - NE1 7RU
e-mail: (E-mail removed)

Start date: 1 May 97
Duration: 12 months - COMPLETED

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It was last updated on 1 July 1999, and is maintained by (E-mail removed)