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Esprit Project 33544 - HSLA
Open LTR - 2 nd phase
( 1 st phase see project 23544 )
A High Speed Logarithmic Arithmetic Unit

Keywords: arithmetic, computer arithmetic, computer architecture, logarithmic number system

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The first phase of this project has demonstrated that LNS arithmetic will offer a substantial speed advantage over existing floating-point devices. In all cases its accuracy is also either equivalent to or better than floating-point, and its complexity is similar. It is the objective of the second phase to bring the LNS hardware system into commercial use, and thereby to enhance the competitiveness of European digital electronics. Specific objectives are as follows.

Phase 1 results indicate that in scientific-type applications a 2 or 3 times speedup is to be expected. Fixed-point applications, while gaining less of a speedup, will benefit from a vast improvement in accuracy, and will become much easier to program.

The approach that we propose is to design a suite of LNS-based arithmetic cells, and to incorporate these into a simple microprocessor. Using these components we will build commercial confidence by producing a series of demonstrators, as outlined above, to provide a direct comparison between LNS and existing techniques. These demonstrators will be based on real commercial examples, and will address areas which are currently based on both ASIC and commodity-microprocessor solutions. A general-purpose development board based on the microprocessor will then be offered for evaluation to OEMs to whom it is likely to be of interest. These organisations will be able to run their own algorithms on the system, and thereby perform an independent evaluation of it. Any organisation wishing to use the system would then be offered the use of the LNS arithmetic cell library to incorporate in their own ASICs.

Broadly speaking, there are two groups of OEMs who use computer arithmetic. For the first, floating-point arithmetic is essential and they therefore use commodity floating-point microprocessors. In doing so, they suffer a restriction on speed which many manufacturers would like to overcome. Only by doing so can they hope to improve their bandwidths or implement better, more complex algorithms. To these users this proposal can offer a speed improvement of 2 to 3 times, whilst maintaining the range, accuracy and complexity of their current floating-point implementations The second group includes those who require high speed and / or low complexity and who therefore design a fixed-point ASIC or buy an equivalent commodity device. To these OEMs we can offer the range and precision of floating-point at a similar speed to fixed-point. These users may see little change in speed, but a vast improvement in accuracy. They would also be able to write their applications more quickly and easily than with fixed-point arithmetic, thereby saving on expensive development time.

As mentioned above, exploitation of these results will follow from successful trials of the system at industrial sites. The participants will (subject to suitable licensing arrangements) be able to use the arithmetic cells in the ir own products. Dissemination of the results by means of conventional publication and publicity events will ensure that we reach as wide a field of potential new users as possible.

Contact Point
Dr J.N. Coleman
The University Newcastle upon Tyne
Dept Electrical and Electronic Engineering
UK - Newcastle upon Tyne NE1 7RU
e-mail: (E-mail removed)

Start date: 1 January 99
Duration: 36 months

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It was last updated on 1 July 1999, and is maintained by (E-mail removed)