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Future and Emerging
Technologies (FET)

Advanced Research Initiative in Microelectronics (started 1996) :
Optoelectronic Interconnects
for integrated circuits: OPTO
Nano-Scale Integrated Circuits:NANO

Melari - NID 7th Workshop - Barcelona - 7 - 9 February 2001
Quantum Information Processing & Communications: QIPC Nanotechnology Information Devices: NID Universal Information Ecosystems:

Optoelectronic interconnects for integrated circuits

Image News Release

Image Conferences

Image 1st Workshop Zürich - October 15-17, 1997

Image 2nd Workshop Israel - October 14-16, 1998

Image 3nd Workshop Athens - October 13-15, 1999

Image 3nd Annual Review Ulm - April 21-23, 1999

Image 4th Annual Review Edinburgh - April 5-7, 1999

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Image Roadmap

Image Steering Committee

Image Working Groups

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This site was last updated 26 October 2000



The serial nature of conventional circuit architectures results in long interconnection lines on the chips, with most of the devices being idle at any one instant. In combination with the continuous downscaling of ICs, this has resulted in electrical interconnects representing a formidable bottleneck to further performance increase sand miniaturisation. Research activities therefore seek to combine optical and electrical interconnects to alleviate some of the above bottlenecks and obtain circuits with higher functionality and better performance. It is also likely that non-conventional circuit architectures, such as hybrid parallel/serial, will be required to take full advantage of optoelectronic interconnects. The emphasis throughout will be on research approaches that could lead to cost effective, manufacturable and practical solutions.

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Five projects have recently been launched. These projects are proposing various hybrid solutions for inter/intra-chip optoelectronic interconnects. Other work concentrates on the monolithic integration of emitter sources on silicon by heteroepitaxial growth of GaAs.

Work on traditional sources such as GaAs VCSELs and LEDs, as well as on alternative sources such as SiGe, porous silicon and Er-doped silicon, will also be carried out to assess the potential for the future development of each technology.

Phase one of the optoelectronic interconnects cluster will last two years. At the end of year one and year two (autumn 1997 and autumn 1998 respectively), an international, open workshop will be organised to present the results.

The projects although contractually independent, are stronly linked for obvious technical reasons. Inorder to make the management of such projects clusters effective, a STEERING COMMITTEE has been created, and WORKING GROUPS across projects on specific topics are formed.

Follow the links below to read the synopses of the five cluster projects:

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News release (updated 28 February 1997)

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For more information, please contact:

Pierpaolo Malinverni

E-mail (E-mail removed)

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Nanoscale Integrated Circuits

Image Introduction

Image Technology Roadmap for Nanotechnolog y: edition 1999

Image Technology Roadmap for Nanotechnology:edition 2000 under preparation - subscribe now

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This site was last updated 20 November 2000



MELARI and NID supports innovative research aimed at the development of new concepts for information processing systems operating at the nano-scale. NID covers any research field that could contribute in shaping future visions for information processing nano-systems, from quantum electronics to nano-mechanics and biology. It gives emphasis to radically new approaches and cross-disciplinary integration. There are three major inter-related specific objectives:

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CHARGE 22953 The Coulomb Blockade Applied to the Realisation of Electronics
Synopsis - Homepage
FASEM 23214 Fabrication and Architecture of Single Electron memories
Synopsis - Homepage
LASMEDS 22955 Fabrication of elementary molecular electronic devices
Synopsis - Homepage
QUADRANT 23362 Quantum Devices for Advanced Nano-electronic Technology
Synopsis - Homepage
QUEST 23274 Quantum Electronics using Scanning Tunnelling microscopy based lithography
Synopsis - Homepage
RSFQ-HTS 23429 High Temperature Superconducting Rapid Single Flux Quantum Logic
Synopsis - Homepage
SIQUIC 22987 Silicon Quantum Integrated Circuits
Synopsis - Homepage
SPIDER 23307 Spin Dependent Nano-Electronics
Synopsis - Homepage
LOCOM 28844 Logic Circuits with Reduced Complexity based on Devices with Higher Functionality
Synopsis - Homepage
SPINUP 29097 Semiconductor Processing by imprint of ultrasmall patterns
Synopsis - Homepage
NANOTECH 28785 Development of Nanoimprinting technique suitable for large area mass production of nm-scale patterns
Synopsis - Homepage
ANSWERS 28667 Autonomous Nanoelectronic systems with extended replication and signalling
Synopsis - Homepage
Q-SWITCH 30960 Electron Waveguides for Quantum-based Switching
Synopsis - Homepage

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Finished Esprit Projects in related areas

Acronym Number Title
MICROGUN 20227 Low-energy coherent electron microguns: Organic microsystems and nanostructures
Synopsis - Homepage
NANCAR 20084 Nanolithography using chemically amplified resists
Synopsis - Homepage
NANOWIRES 23238 Conductance characteristics and mass fabrication of Nanoscale integrated circuit nanowires
Synopsis - Homepage
QUANTECS 6312 Quantised Electronics - Devices and physical phenomena with potential application in the processing, storage and transmission of information using single electrons and photons
LATMIC II 6536 Lateral Microstructures: Fabrication, Low Dimensionality Effects and Application to III-V Devices
NANOPT 6719 Nanometre Structures for Future Optoelectronic Applications
ADEQUAT 7236 Advanced Developments for 0.25 micron CMOS Technologies
SOLDES 7260 Self-Organising Low-Dimensional Electronic Structures
SMALL STRUCTURES 8050 Novel Phenomena in Small Structures
PRONANO 8523 Processing on a Nanometre Scale
SMART 8659 Surface Memories Using Atomically Resolving Techniques
SETTRON 9005 Single Electronics; Electronic properties of ultraminiature semiconductor and metal structures in 10nm range
NOVA 9159 Novel Architectures for 0.18 micron Devices
(project running until 31-12-99)
22495 The vertical advanced heterojunction MOS transistor as a building block for CMOS from the year 2000 on
Synopsis - Homepage

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Contact Person:

Ramón Compañó
European Commission DG INFSO - F1
IST Programme - Future and Emerging Technologies
E-mail : (E-mail removed)

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This document is located at /esprit/src/melari.htm
It was last updated on 29 November 2000, and is maintained by
Pierpaolo Malinverni - E-mail: (E-mail removed)
Ramón Compañó - E-mail : (E-mail removed)