This project concerns the design of an application specific processor for the implementation of the lower layer functions of the ISDN protocol standard. The coparis concept will enable the production of ISDN components conforming to ISDN standards of ITU and ANSI such as I.430, G.961-T1.601, DS-1 and G.703.
Further, it will provide an open programming interface, thus facilitating the support of future standard and / or proprietary ISDN interfaces. The proposed architecture will form the baseline technology for the next generation of commercial ISDN components for both the basic rate and the primary rate ISDN market, targeting lower production cost and improved integration. The architecture will specifically include the capabilities of new processors, which are at the edge of the state-of-the-are in the telecom area.
The proposed architecture will integrate a processor core together with application specific functions. These functions will be delivered as a set of reusable hardware (macrocells) and software functions. Further, appropriate analogue and digital circuit blocks will allow the seamless interconnection to various ISDN line interfaces with minimal external circuitry.
The project will investigate the various line coding algorithms in terms of complexity and general appropriateness to embedded implementation. Further, the project will investigate standards closely related to applications involving ISDN standards, such as the multimedia transport related standards H.2xx. The project will provide the roadmap for their implementation into COPARIS compliant components.
The project will also deliver an application specific component based on the COPARIS architecture. The component (the Universal ISDN transceiver - UNIST) will implement a subset of ISDN interfaces in wide use, thus demonstrating the strength of the COPARIS architecture on a particular realization case.
In order to achieve the specified goals, the project will exploit the latest technology advanced in the OMI area, by integrating several functions in a single component ( a microprocessor core with enhanced DSP functions, sophisticated analogue signal conditioning circuits, analogue to digital conversion circuits, large on-chip ROM and RAM, flexible serial and parallel digital system interfaces and power management features addressing low-power applications).
Start date: October 1997
End date: September 1999
Tel: 0049 89 636 23877
Center for Communications Systems Research - University of Surrey (United Kingdom)
National Technical University of Athens (Greece)