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Image VHDL Simulator Redefines Performance Levels

VISE is a powerful high performance and high capacity VHDL simulator, currently benchmarking at 10 times the performance of the best commercially available simulators, allowing dramatic reductions in product development cycles.


The quality and development time of any electronic product depends greatly on the degree of simulation that can be performed during the design phase. Therefore, the power and efficiency of the simulator is of paramount importance. As a result of the AIDA project, which included research by ICL into powerful simulation algorithms and scheduling methods, ICL has developed an extremely powerful simulator for VHDL designs. Known as VISE, it provides the power and simulation performance required for real system level designs, providing approximately 10 times the performance of any other commercially available VHDL simulator at the Register Transfer Language (RTL) level or above. This translates into the ability to achieve a greater amount of simulation in a given time, helping achieve the best design, first time and on-time.

Business perspective

The business potential of simulation systems is well documented. More simulation means improved designs and, by allowing earlier prototyping with fewer bugs, also reduces development costs. Extremely powerful VHDL simulators such as VISE have a major impact on a company's competitiveness, greatly reducing design times and thus the time-to-market, which is especially critical in many emerging multimedia and communications markets where the first company with a product will often establish a dominant position. It also allows manufacturers to ensure designs of electronic systems are right first time, eliminating the cost and delay of re-working from development plans. Although currently not available on the market, VISE is a commercial quality tool which will soon be released through a computer aided design (CAD) vendor channel and is expected to become the simulator for VHDL designs.

Technical perspective Image

The simulation technology used in VISE includes unique optimisation for higher levels of VHDL specification and highly efficient use of memory, allowing models of very large systems to be built without the need for extra hardware investment. Independent module compilation facilities and support for hierarchical design methods give a flexible but controlled approach to system development. VISE also incorporates a powerful visualisation tool which provides a flexible, interactive environment for design verification.


The VISE simulator is currently being used by ICL for the design of High Performance Systems and the company's first design incorporating 10 million gates has already been completed. During the design of this system, the amount of design simulation time achieved was 10 times that previously achievable with other simulators. It is expected these dramatic simulation time improvements will eventually lead to achieving the residual design error rate of 2 parts per million.

Contact Point

Jim Heaton or Steve Hodgson
Wenlock Way West
M12 5DR

e-mail : (email removed)


Research Area Technology and Components for Subsystems

Project AIDA

Keywords design verification; simulation; VHDL simulator;

Project Participants
Bull FR
SGS-Thomson FR
Siemens GE

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