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Report of the Silicon Technology Workshop
17 October 1997, Brussels
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A
TTENDEES
J. Bruchez SiTec, UK
M. Graef Philips, NL
N. Lehner Siemens, D
E. Martinez Lucent, E
M. Montier SGS Thomson, F
H. Forster EC
D. Beernaert EC
M. Boukerche (rapporteur) EC
G. Kelm EC
INTRODUCTION
This report summarises the main discussions and conclusions of the Industrial Workshop on Silicon Technologies held on 17 October 1997 in Brussels.
The workshop brought together representatives from major silicon device manufacturing companies in Europe. The presentations made by the contributors, as well as the open and stimulating follow-on discussions, provided information on the required evolution of silicon processing and equipment technologies in order to match the future needs of their companies.
The information presented will contribute to the definition of the Framework IV 1998 workprogramme, and provided valuable input for the elaboration of the future Framework V workprogramme.
SILICON TECHNOLOGY TRENDS
The pace of technology improvement is accelerating faster than the Moore’s law, with technology generation cycles becoming shorter than 3 years.
This situation should last for the next coming years until deep UV 193nm optical lithography is expected to reach its limits around 0.1um feature size in 2003. The development of DUV optical lithography therefore requires special attention to reach these limits.
The developments of process module and equipment are getting tightly interdependent. The equipment maker is now expected to provide the process module together with the equipment itself. Beta users contribute to equipment validation, and process module development. In return they have early access to new process technologies.
The trend enlightens further the importance of strong user-supplier relationships in line with the mission of the semiconductor equipment assessment (SEA) EC initiative.
The customer is expecting ever higher functionality at the same or lower price.
300mm (or higher) silicon wafer diameter equipment and processes will decrease manufacturing costs and increase throughput. Process reliability should be also improved since the capital value of wafer lots in production increases dramatically with wafer size.
The use of in-situ metrology for better process monitoring and control will gain importance.
The cost of process development and capital equipment is sky rocketing, motivating company alliances for development and manufacturing, and convergence to single process module solutions.
The one dimension parameter description of Si technology improvement based on the minimum transistor gate length is still valid for lithography, but should be complemented by other technology criteria related to dielectric materials and interconnects since they will become key limiting factors to overall performance.
The limits of classical transistor operation due to shrinking geometries are not expected to be reached before 2015.
The main technology challenges for the coming years are expected to be the followings:
- Lithography for 0.1um dimension and below for industrial production.
A technology bottleneck is expected around 2003 when the limits of DUV optical lithography (193nm) should be reached. An important development effort is needed to bring the limits of optical lithography down to 0.1µm feature size in production.
Beyond 0.1µm, EUV optical technology will be extremely challenging, with such requirements as rectification of optical surfaces with atomic dimension precision across macroscopic lens diameters. The corresponding metrology tools for component making, mask and process control, will also be required.
Such large developments will benefit from world-wide cooperation.
- Interconnect architectures for 0.15um and below.
With shrinking dimensions, the resistivity of and capacitive coupling between metal layers become limiting factors in RC time constants. Copper interconnects with damascene chemico-mechanical polishing etching/planarisation are required. The process will depend on reliable copper encapsulation to avoid silicon contamination.
- Low dielectric constant insulating materials
Also to limit RC time constants, low K insulating materials are needed in between metal layers to limit parasitic capacitance in back end interconnects.
- Integrated process modules / equipment able to offer increased productivity with 300mm wafer size handling, but also for main stream 200mm wafer size.
- High dielectric constant materials
With shrinking dimensions the thickness of the SiO2 gate oxide will reach a limit when tunnelling current through the insulator will become non-negligible. High performance insulators with high K, high charge and electric field to breakdown, and low surface states, will be required for high capacitance gate to channel coupling and large transconductance without gate leakage.
- Front end architectures for 0.1um and below
pushing the classical transistor operation closer to the limits with shrinking dimensions are needed.
- Other materials
Use of other new materials like selective Epitaxy of silicides, high mobility SiGe channels, low workfunction and undepleted gate materials, can simplify the overall process and improve performance.
- Mixed analogue/digital high frequency CMOS
is becoming possible thanks to performance increase with shrinking dimensions. It will open new possibilities for Telecom applications.
- Advanced embedding options
like volatile/non-volatile memory, RF/ low power blocks are needed for complex "system on a chip" applications.
- Low power / high performance silicon on insulator
is an emerging technology, still requiring substantial work on substrate materials and modelling.It should become more competitive with shrinking dimensions and is ideally suited to portable applications.
CONCLUSION
The pace of technology evolution is increasing faster than anticipated earlier. The limits of DUV optical lithography have to be investigated in order to keep up with the expected evolution till 2003.
Critical process steps and new equipment developments like for 300mm wafer processing, are merging, further motivating strong user-supplier relationships on a world basis like in the SEA initiative for validation and dissemination. The development of the equipment itself is expected to be beard by industry.
Back end interconnects involving new materials like dielectrics and processes like copper damascene metalisation and CMP are becoming crucial to device architectures and performance for 0.15um and below. They can also reduce process complexity and increase yield.
New front-end architectures able to push forward the limits of classical transistor operation below 0.1um should be pursued.
Full process integration and production introduction is considered to be the responsibility of industry.
SOI technology is emerging, and offers a high potential for low power/high performance applications in the future.
The ever-increasing cost of R&D motivates companies to sign technology agreements and share the investments and risks.
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