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the 7th Framework Programme 2007-2013 on our FET Proactive - FET Open Web sites.
Advanced Computing Architectures (ACA)
Proactive Initiative in the 6th Framework Programme
News
- CASTNESS’08: Computer Architectures and Software Tools for Numerical Embedded Scalable Systems" -
Workshop and School 15 - 18 January 2008 - Roma (IT) CASTNESS'08 preparation - CASTNESS home page
What is Advanced Computing Architectures (Workprogramme text)
New computing architectural developments together with a new generation of compiling and operating systems are required for general purpose, programmable or reconfigurable systems addressing projected computing, storage, and communication needs of future applications in a 10+ years timeframe.
The aim of this programme is to develop novel advanced computing architectures, methods, tools and intellectual property that will:
- Substantially increase the performance of computing engines (processors and scalable systems made of multiple processors) well beyond projected performance of Moore's law (e.g., by two orders of magnitude), while reducing their power consumption.
- Provide leading compiler and operating system technology that will deliver high performance and efficient code optimisation, just-in-time compilation, and that will be portable across a wide range of systems.
- Constitute building blocks to be combined with each other and programmed easily and efficiently, even in heterogeneous processing platforms.
The following long-term research themes should be addressed:
- Processor architectures: low power, low-cost or high-performance processors, application-oriented processors (embedded computing, multimedia, networking, wireless, etc), including programmability and reconfigurability.
- Scalable multiple processor system architectures: cluster, SMP, chip-MP, tiled architectures, storage and interconnection architectures, high-performance embedded computing architectures.
- Retargetable optimisation, compilation for multi-core systems, generation of code with guaranteed security properties, automated compiler generation, architecture and operating system cross-optimisation, architecture-aware compilation, and optimisation of high-level language for embedded systems.
- System architecture tools for heterogeneous parallel design of highly complex computing architectures.
- Highly flexible operating systems that will provide a unified programming model for computing systems at different scales, as well as across different heterogeneous subsystems.
The proposed programme is expected to mobilise key research stakeholders. Participation from industry is required in order to address research directions that have the potential of providing the required application breakthroughs (ranging from tiny embedded or wireless systems to large internetworked server-based systems) in a 10+ years horizon.
- Workprogramme text (PDF, 14KB)
- Terms of Reference (PDF, 49KB)
Projects
3 Integrated Projects funded via the 4th IST call
- AETHER: Self-Adaptive Embedded Technologies for Pervasive Computing Architectures
- SARC: Scalable Computer Architecture
- SHAPES: Scalable software Hardware Architecture Platform for Embedded Systems
Related Actions - Events
- Workshop: Computer Architectures and Software Tools for Numerical Embedded Scalable Systems: CASTNESS'07; 15-17 January 2007 - ROMA - Italy
- Flyer CASTNESS'07 (PDF, 1109KB)
Brainstorming meeting - 13th October 2003
A brainstorming meeting was held in Brussels on 13th October 2003, for defining the main challenges and key research directions on future high-performance computing architectures with a 10+ year horizon.
- Final report (PDF)
- Opening
- Thierry Van der Pyl - Head of Unit FET - Eur. Commission (PDF)
- Presentations (PDF)
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- David Bernstein - IBM Haifa
- Uwe Brinkschulte - University of Karlsruhe
- Abey Cohen - Bar-Ilan University
- Marco Cornero - ST-Microelectronics
- Martin Danek - Czech Technical University, Depart. of Comp. Science and Engineering
- Koen De Bosschere - University of Ghent, Elis Depart.
- Geert Deconinck - KU Leuven, Esat
- Gilbert Edelin - THALES
- Phil Edworthy - ARC
- Jakob Engblom -VIRTUTECH
- Krisztián Flautner - ARM
- Gert Goossens - TARGET Compiler Technologies
- Manolis Katevenis - FORTH
- Stefanos Kaxiras - University of Patras
- Michael O'Boyle - University of Edinburgh
- Pier Stanislao Paolucci - INFN and ATMEL/IPITEC
- Andy Pimentel - University of Amsterdam
- Alex Ramírez - UPC Barcelona
- Henk Schepers - PHILIPS
- Marius Schoorel - ACE
- Gerard Smit - Universtity of Twente
- Per Stenström - Chalmers University of Technology
- Olivier Temam - Paris South University (CNRS & INRIA)
- Steve Thompson - XYRATEX
- Mateo Valero - UPC BARCELONA
- Olle Viktorsson - ERICSSON
Contacts
For further information please feel free to contact:
- Patrick Van Hove
Tel.: +32-2-29 68106 - Werner Steinhoegl
Tel.: +32-2-29 50080
Fax: +32-2-29-68390
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Timetable
- FET Infoday: 13 Jan 2005, Brussels- Presentations
- 4th IST Call launched: 01 Dec 2004
- Deadline for proposals: 22 Mar 2005, 17:00 (GMT+01:00)
- Start of projects: early 2006