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2003-2004 Work Programme
2.3.1.1 Pushing the limits of CMOS and preparing for post-CMOS
Objective: To develop, ahead of the ITRS international roadmap, semiconductor devices shrunk by an order of magnitude down to the 5 nm size, and alternative devices for the post-CMOS era. Research will also aim at enabling the design in-time and at cost, of reliable 1 billion gate systems-on-chip or systems-in-package, improving productivity by a factor of 10 by 2010. This will help prepare for the electronic components of 2010 and beyond.
For technologies, the focus is on
- Integration of advanced and non-CMOS devices into the basic silicon technologies and new on-chip wiring to minimise signal propagation delays at nanoscale;
- Driving the performance of silicon-based and of compound semiconductor devices to facilitate ultra high frequency and high power applications and to accelerate integration of micro and opto-electronics including related packaging technologies;
- Pushing the limits of lithography including mask-less pattern transfer technologies, and mask making technologies ;
- Acquisition of knowledge and control of emerging nanoelectronics technologies, with potential of high device performance and low cost of mass production for future applications, and provision of better environmental, safety and health conditions;
It is expected that work on the above topics would crystallise around Integrated Projects on e.g. "nano-CMOS", the "high frequency challenge" or "lithography". These may include equipment assessment actions. Networks of Excellence should help structure research in "new devices" and "advanced lithography". It might be necessary to complement major investments by industry in advanced research infrastructure, to achieve the ambitious research goals above.
For design methods and tools, the focus is on
- Providing novel approaches to design better and faster at system level. The major challenges are to maintain or improve system performance and reliability, to specify and verify at system level, to stimulate IP (Intellectual Property) reuse, to optimise power consumption, and to enhance flexibility and reconfigurability;
- Devising methods to improve the use of large systems by including redundancy or to improve the testability, in particular with self-test circuits;
- Addressing specific challenges in design with new methods and tools. These include mixed-signal design, low power design, RF circuits and packaging;
- Supporting the industry in the change from board electronics to system-on-chip and complementing the design activities with education and training in modern design practice. Developing, demonstrating or standardising architectures and methods improving the design productivity is also needed.
It is expected that work on the above topics would crystallise around Integrated Projects on e.g. "system-level SoC design" or "reconfigurable systems". The Integrated Projects are expected to include complementary user involvement. Networks of excellence should help structure the European research effort in "SoC design standardisation and training".
For both, technologies and design tools, topics complementing this overall strategy could come forward through the other instruments but should strictly be focused on promising alternative approaches.
Work should, where appropriate, precede and complement work implemented under EUREKA/MEDEA and in initiatives at member and associated state level. The work might also be complemented by major industrial investments thereby demonstrating value for money and that the proposed actions fit in an overall strategy. Activities should contribute to the intellectual property portfolio and to the knowledge that will enable Europe to compete internationally.