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2005-2006 Work Programme
2.4.1 Nanoelectronics
Objectives
The technical goals are to reduce the transistor size deep into the nano-scale, to radically transform the process technologies through the integration of a large number of new materials, and to master the design technologies for achieving competitive systems-on-chip and systems-in-package with increasing functionality, performance and complexity. This should be obtained without compromising on reliability, energy consumption and costs of such systems. The aim is also to secure the necessary design skills and stimulate the use of technologies in areas where these are insufficiently used. The work supports, and is in line with the orientations proposed by the Technology Platform 1 on nanoelectronics.
Focus
The SO covers research work on process and device technologies and on design technologies of nanoelectronics integrated circuits.
- For process and device technologies, the focus is on:
- New materials integration and the related innovative processes to improve miniaturisation, performance, and cost of the next generations of non-conventional silicon-based devices (mid-term and long-term) for generic logics, memories, analogue, RF and high power platforms.
These tasks are to be addressed by means of IPs and/or STREPs enabling strong collaboration and complementarity between academia and industry.
- Equipment and materials R&D activities (short-term and mid-term) and assessment actions (innovation activities with specific evaluation criteria) 2 for the manufacturing of the next generations of chips. Lithography has already been adequately covered in previous FP6 calls for proposals.
These tasks are to be addressed by means of IPs with strong collaboration between users and suppliers, and significant involvement of SMEs.
- New materials integration and the related innovative processes to improve miniaturisation, performance, and cost of the next generations of non-conventional silicon-based devices (mid-term and long-term) for generic logics, memories, analogue, RF and high power platforms.
- Design technologies cover methods, tools and architectures for designing advanced nanoelectronic circuits within economical and technical constraints. The focus is on research for :
- Mastering the design complexity and increasing the design productivity for system-on-chip (SoC) or system-in-package (SiP). This notably involves work on application and design platforms, Intellectual Property reuse, verification and post-fabrication tests, reconfigurable structures, system-on-chip architectures and design flows.
- Mastering the technological shortcomings of nanoelectronics such as unreliable device behaviour, dispersion of circuit parameters, parasitic and interconnect effects, and leakage currents.
- Addressing specific "high value" design and test competences that are essential for the strategic European application areas. These include for example analogue and mixed signal, high frequency and RF circuits, smart power and low power.
- The three tasks above are to be addressed by means of IPs and STREPs both with involvement of users. Participation of SMEs is encouraged.
In addition there is a need for complementary measures, in particular:
- Access services supporting academic research on design as well as university education of qualified designers through access to industrial design tools and multi-project wafers. Access services are to be addressed by means of SSAs.
- Stimulation actions3 aim at increasing the interest of students and improving the quality of education in SoC design. This will be done through IPs that emphasize research carried out by, and training of, students in SoC design.
It is expected that stimulation actions and in particular access services are to a significant extent financed through own resources or receipts from third parties.
- Use actions4 should promote the integration and use of micro- and nanoelectronics technologies (limited to reconfigurable systems) in SME products and in application and/or geographical areas where these technologies are insufficiently used. They cover awareness actions, the development and evaluation of industrial test cases, and the dissemination of results for replication.
IPs will be the instrument for use actions.
- SSAs and CAs can be used to promote joint work with national programmes and Eureka, to support the work of the Technology Platform on Nanoelectronics, to define future research agendas, or to identify emerging topics and research groups world-wide.
With regard to design technologies, the SO focuses on chip design including SoC and SiP, and is complementary to the SO "Embedded Systems" which focuses on system design.
- Instruments:
- see above.
- Indicative budget:
- IPs: 80%; STREPs, CAs, SSAs: 20%
- Up to 50% of the total pre-allocated budget for this strategic objective may be devoted to design-related activities provided that projects of high quality are submitted.
- Call information:
- IST Call 4
1 Information about the European Technology Platform for Nanoelectronics is available from /ist/eniac
2 Assessment actions are a specific type of IP. They deal with the assessment of prototype equipment and materials in state-of-the-art manufacturing processes, shall be led by the user organisations carryng out the assessments, and may set aside a budget for adding further assessments that have not been identified at proposal stage. Such proposals should be clearly identified as an "assessment action" in the proposal sub-title and in the keyword box of the form A1. The IP's "S&T excellence" sub-criterion of "clear progress beyond the current state-of-the-art" will be evaluated as "the extent of innovation in manufacturing processes"
3Stimulation actions are a specific type of IP. Such proposals should be clearly identified as "stimulation action" in the proposal sub-title and in the keyword box of the form A1. The IP's "S&T excellence" sub-criterion of "clear progress beyond the current state-of-the-art" will be evaluated as "the extent of increase of knowledge and skills"
4 Use actions are a specific type of IP. Such proposals should be clearly identified as "use action" in the proposal sub-title and in the keyword box of the form A1. The "S&T excellence" subcriterion of "clear progress beyond the current state-of-the-art" will be evaluated as "the extent of product innovation by using the technology"