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Case Study: Breaking the Size Barrier

Will the predicted annual doubling of the number of transistors per chip finally hit the buffers around 2010? An Esprit project is finding ways to keep Moore's Law on track.

A 10nm silicon island. Tübingen University

Nanocrystals in a silicon dioxide layer.

Electrodes, with 1nm metallic grains.

Moore's prophecy referred to logic chips. But the density of memory chips has also grown geometrically, and they likewise face the imminent termination of this explosive increase in speed and power.

Feature sizes less than 0.05 microns (50 nanometres) cannot be resolved by optical lithography, the technology used to print circuits on today's chips. In any case, circuits this small suffer from problems of efficiency and reliability, caused by the unpredictable behaviour of electrons at the nanometre scale.

This poses a major problem for the microelectronics industry. Looked at another way, it presents a huge opportunity - for whoever is first to adopt a new technology when the limits of the present one are eventually reached. The Advanced Research Initiative in Microelectronics (MEL-ARI) of the Esprit programme aims to equip Europe to seize this opportunity. In particular, the 12 projects of the Nano-scale Integrated Circuits cluster focus on overcoming current limits to miniaturisation.

"Right now, the random behaviour which appears at the nano-scale is seen as a constraint," says Kostas Glinos of the Esprit programme. "The challenge is to find ways to exploit it."

Island-Hopping Electrons

FASEM (Fabrication and Architecture of Single Electron Memories) aims to establish a technological platform for mass-production of memory chips which consume far less power than today's DRAMs, and have a capacity at least an order of magnitude greater - around one terabit per cm2. Led by Dr Huguette Launois of CNRS-L2M in Bagneux, France, the project's partners are exploring five parallel approaches, all based on single electron charging effects.

In DRAM, a bit of data is stored in a capacitor, which is charged to represent a '1' and discharged to represent a '0'. Tens of thousands of electrons are transferred and stored. "We are trying to do the same job using precisely controlled flows of fewer than 100 electrons," says Launois. "This relies on features just a few nanometres across. Data is written and read as tiny changes to the electrical potential in an array of these islands."

Tübingen University has created single 10nm silicon islands by lithography, etching and oxidation. The Institute of Microelectronics (IMEL) in Athens has produced 3nm silicon nanocrystals in a silicon dioxide layer by implantation and annealing. Dr Launois' own L2M team has built a Coulomb Blockade device by coupling high-resolution lithography with the self-organised deposition of 1nm metallic islands. The Microelectronics Research Centre in Cambridge has created a polysilicon wire in which small islands are defined by natural defects. CNRS-GPEC in Marseille employs scanning tunnelling microscopy (STM) to induce the local chemical vapour deposition of metallic islands.

The project's other two partners - IMEC in Belgium and Hitachi Europe in the UK - are working on CMOS integration and system architecture respectively. "Although these devices use entirely new principles, they are the direct heirs of existing silicon technology, and fully compatible with it," Launois explains. "We want to be ready to integrate our memory into the conventional CMOS environment."

She warns that final success is still not certain, but hopes to be ready to meet the demand for high-capacity memory around the year 2010.

Contact:
H. Launois, CNRS-L2M
Tl. +33 1 42 317 240
Fx. +33 1 42 317 350
E-m. huguette.launois@l2m.cnrs.fr

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