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FP6 project to keep EU at forefront of nanoelectronics [Print to PDF] [Print to RTF]

In an effort to keep Europe at the forefront of nanoelectronics, the European Commission is providing 24.17 million euro for a new project aimed at pushing the limits of semiconductor performance and density.

The NanoCMOS (Complementary Metal Oxide Semi-conductor) project rep...
FP6 project to keep EU at forefront of nanoelectronics
In an effort to keep Europe at the forefront of nanoelectronics, the European Commission is providing 24.17 million euro for a new project aimed at pushing the limits of semiconductor performance and density.

The NanoCMOS (Complementary Metal Oxide Semi-conductor) project represents an attempt to allow scaling (arrangement in a graduated series) to continue. It therefore strives to pioneer the necessary and revolutionary changes in materials, process modules, device architectures and interconnections, as well as the related characterisation, modelling and simulation work, necessary to go from a 45-nanometer CMOS node to a 32-nm one.

'NanoCMOS is a broad project focusing on the research and development (R&D) activities necessary to develop the 45-nm, 32-nm and more advanced CMOS manufacturing processes, with the exception of lithography,' explain the project partners, which include Europe's three leading commercial chipmakers: STMicroelectroics, Philips and Infineon, as well as research institutes and small and medium-sized enterprises (SMEs).

The partners are currently preparing for the second phase, in which the developed technologies will be validated in an industrial environment.

NanoCMOS has three main objectives. The first is to demonstrate the feasibility of front- and back-end 45-nm CMOS logic process modules. In order to achieve this, the partners intend to process an aggressive SRAM chip as a demonstrator, displaying worldwide best characteristics and an advanced two-level metallisation structure by the end of 2005.

The second objective is to perform exploratory research on critical aspects of the materials in preparation for the 32 nm and 22-nm process nodes. A demonstrator will be established for this next node sometime in 2007.

Finally, the third objective of the project is to take the results of the first objective and generalise the process to produce a 45-nm CMOS logic process resulting in the fabrication of the commercial complexity chips on 300-mm diameter wafers. This goal should also be achieved before the end of 2007.

Alongside this project, a 'Network of Excellence' has been created to bring together the best European semiconductor research teams in order to formulate a research programme that is complementary to the needs of NanoCMOS.

As Guillermo Bomchil, NanoCMOS project leader explains, 'together Nano CMOS and SiNano cover the whole domain of silicon microelectronics from the 45-nm node down to what experts believe would be the limits of CMOS.'

'This project is ambitious,' he concluded. 'European technology companies are often behind their Japanese and American counterparts. Europe was not able to meaningfully participate in the microelectronics boom of n the 1970s and 1980s, and European governments are determined not to miss the boat on the next 'nano' revolution.'
Source: The NanoCMOS consortium

Related information

Record Number: 24055 / Last updated on: 2005-06-28
Category: Project
Provider: EC