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Tiny and tinier: EU projects minimise size of semiconductor chips [Print to PDF] [Print to RTF]

Two EU-funded projects have been pushing the limits of chip miniaturisation, trying to make complementary metal-oxide semiconductor chips (CMOS) even smaller than they already are. While the NanoCMOS project, which was completed in 2006, helped develop 45 nanometre (nm) node s...
Tiny and tinier: EU projects minimise size of semiconductor chips
Two EU-funded projects have been pushing the limits of chip miniaturisation, trying to make complementary metal-oxide semiconductor chips (CMOS) even smaller than they already are. While the NanoCMOS project, which was completed in 2006, helped develop 45 nanometre (nm) node semiconductors, its follow-up project PULLNANO is aiming at 32nm and ultimately 22nm features.

'The semiconductor industry is in the business of selling square millimetres of silicon,' states Gilles Thomas, the director of R&D cooperative programmes at French semiconductor manufacturer STMicroelectronics, coordinating partner of the two projects. 'So, by cramming more transistors into a chip you're delivering more capacity, more functionality and more computing power for the same price. It's why things like mobile phones, LCD TVs and DVD players are coming down in price.'

Chips most commonly used in products today have features between 65 and 90nm in size, about 1,000 times smaller than the width of a human hair. However, project partners think that there is still considerable room for further miniaturisation, until it will cease to be profitable - probably around the 16 to 11nm mark, Mr Thomas estimates. This point has not been reached yet though and, if Mr Thomas is right, it will not be reached for another 12 to 15 years.

Currently, the real limit to computer processor performance is a quantum mechanical effect known as gate leakage, where mobile charge carriers such as electrons tunnel through insulating regions within the chip. This leakage increases exponentially as thickness of the insulating region decreases.

The PULLNANO researchers have tackled this problem by using a hafnium-compound-based insulator to replace traditional silicone dioxide. According to Mr Thomas, they have achieved a 100-fold reduction of gate leakage as a result.

Despite this preliminary success, STMicroelectronics does not expect to start commercialising the first fruits of the PULLNANO project before 2011. The results of the forerunner project NanoCMOS, in contrast, may find their way into consumer electronics by as early as 2009.

NanoCMOS involved 20 partners and had more than EUR 24 million in funding under the Sixth Framework Programme (FP6) at its disposal. The total project cost amounted to about EUR 46 million.

Some 38 partners contribute to PULLNANO, which receives similar financial support. Both projects have helped give Europe an edge in semiconductor manufacturing, Mr Thomas suggests. He notes that the highly competitive sector does however remain dominated by American and Asian giants such as Intel and Samsung. Nonetheless, there is plenty of room for future growth, even as chips become cheaper.
Source: ICT Results, PULNANO project

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Record Number: 28948 / Last updated on: 2008-01-09
Category: Project
Provider: EC