MeshAnalyzerProject ID: 662704
Finanziato nell'ambito di:
H2020-EU.2.3.1. - Mainstreaming SME support, especially through a dedicated instrument
Analysis Tool for Mesh Design of Leading Edge Design of Integrated Circuits
Dettagli del progetto
Costo totale:EUR 71 429
Contributo UE:EUR 50 000
Argomento (i):ICT-37-2014-1 - Open Disruptive Innovation Scheme (implemented through the SME instrument)
Invito a presentare proposte:H2020-SMEINST-1-2014See other projects for this call
Meccanismo di finanziamento:SME-1 - SME instrument phase 1
EDXACT (Electronic Design Automation: Extraction Analysis and Control Tools) is a software editor producing software tools that are necessary for the design of leading edge integrated circuits (IC). EDXACT is a supplier of Apple, Samsung, Huawei, Intel, AMD, TSMC and many other companies that supply the world with products containing advanced integrated circuits.
The design of circuits with several tens of millions of transistors has become a normality over the last decade. The feature sizes of leading semiconductor circuits vary from 28nm downto 10nm and are extremely small. The design automation tools proposed by the oligopoly of the major suppliers of the market are lagging behind the technical possibilities. One of the most important aspects is the clock-design, where as much as 40% of design time could be saved by switching to modern tools. More importantly, by changing to a slightly different design approach and using a mixture of a clock-tree and clock meshes, today’s circuits could save energy by more than 35%. Unfortunately, no commercial tools exist today capable of analysing clock meshes correctly. Designers are limited to manual design and internal tools, which is limiting the use of this technology.
We see an important market opportunity for EDXACT by combining our existing technology with existing tools and some intelligent glue in order to create the sought-after mesh analysis tool. Being in direct competition with the leaders of the market, we intend to progressively displace the usage of the monopolistic tool for timing analysis.
Phase 1 of the project will put in place the prototype, including documentation and marketing material, finalize an official partnership with two leading IC manufacturers, and will clarify the business plan for this interesting technology.
Contributo UE: EUR 50 000
Parc Work Center, 8 route des bois