EXTRAProject ID: 671653
Finanziato nell'ambito di:
Exploiting eXascale Technology with Reconfigurable Architectures
Dettagli del progetto
Costo totale:EUR 3 989 931,25
Contributo UE:EUR 3 989 930,50
Argomento (i):FETHPC-1-2014 - HPC Core Technologies, Programming Environments and Algorithms for Extreme Parallelism and Extreme Data Applications
Invito a presentare proposte:H2020-FETHPC-2014See other projects for this call
Meccanismo di finanziamento:RIA - Research and Innovation action
To handle the stringent performance requirements of future exascale High Performance Computing (HPC) applications, HPC systems need ultra-efficient heterogeneous compute nodes. To reduce power and increase performance, such compute nodes will require reconfiguration as an intrinsic feature, so that specific HPC application features can be optimally accelerated at all times, even if they regularly change over time.
In the EXTRA project, we create a new and flexible exploration platform for developing reconfigurable architectures, design tools and HPC applications with run-time reconfiguration built-in from the start. The idea is to enable the efficient co-design and joint optimization of architecture, tools, applications, and reconfiguration technology in order to prepare for the necessary HPC hardware nodes of the future.
The project EXTRA covers the complete chain from architecture up to the application:
• More coarse-grain reconfigurable architectures that allow reconfiguration on higher functionality levels and therefore provide much faster reconfiguration than at the bit level.
• The development of just-in time synthesis tools that are optimized for fast (but still efficient) re-synthesis of application phases to new, specialized implementations through reconfiguration.
• The optimization of applications that maximally exploit reconfiguration.
• Suggestions for improvements to reconfigurable technologies to enable the proposed reconfiguration of the architectures.
In conclusion, EXTRA focuses on the fundamental building blocks for run-time reconfigurable exascale HPC systems: new reconfigurable architectures with very low reconfiguration overhead, new tools that truly take reconfiguration as a design concept, and applications that are tuned to maximally exploit run-time reconfiguration techniques.
Our goal is to provide the European platform for run-time reconfiguration to maintain Europe’s competitive edge and leadership in run-time reconfigurable computing.
Contributo UE: EUR 530 296
SINT PIETERSNIEUWSTRAAT 25
Contributo UE: EUR 420 000
Technical University of Crete Campus - Kounoupidiana
Contributo UE: EUR 559 080
SOUTH KENSINGTON CAMPUS EXHIBITION ROAD
SW7 2AZ LONDON
Contributo UE: EUR 451 250
PIAZZA LEONARDO DA VINCI 32
Contributo UE: EUR 533 836
Contributo UE: EUR 476 250
Contributo UE: EUR 415 000
Down Place 1
W6 9JH London
Contributo UE: EUR 305 812,50
Contributo UE: EUR 298 406
TRINITY LANE THE OLD SCHOOLS
CB2 1TN CAMBRIDGE