Objetivo Conventional analog Phase-Locked Loop (PLL) occupies large area and is difficult to be reconfigured due to a bulky loop filter. In 2005, phase-domain all-digital phase-locked-loop (ADPLL) was proposed. It measured output phase of digitally controlled oscillator (DCO) using a time-to-digital converter (TDC). Unfortunately, designing fine-resolution TDC and wide dynamic range is power-consuming. In this project, instead of utilizing single sampling point per reference clock, we propose to oversample and digitize oscillator oscillator waveform which will produce enough digital samples to reconstruct, now in digital domain, the waveform and compare against a model waveform which will give precise frequency/phase and amplitude information. Thus, it is called, wave-locked loop (WLL) that will result in low-in-band phase noise, fast lock time, and wide-loop bandwidth that is no longer limited by reference clock. Preliminary data shows finer than 1-degree phase resolution even with 10% delay error in sampling clocks, and distortion from input waveform. This shows possibility to break the tradeoff in traditional TDC and improve robustness over PVT variations. Moreover, the design of building blocks which includes low-flicker-noise mm-wave LC Digitally-Controlled Oscillator (DCO) and small-sized ring oscillator with phase noise filtering will be investigated. Thus, this fellowship program studies an innovative frequency synthesizer and clock generation systems using wave-locked loop, which includes the study of oversampling of oscillator waveform for fine phase detection, the study of phase-noise reduction in ring oscillator using discrete-time filtering, the study of mm-wave oscillator with flicker noise corner reduction, and system integration for wave-locked loop system. The proposed synthesizer will be tapeout using advanced CMOS technology and will be measured to verify their performance. Ámbito científico engineering and technologyelectrical engineering, electronic engineering, information engineeringinformation engineeringtelecommunicationstelecommunications networksmobile network5Gengineering and technologyelectrical engineering, electronic engineering, information engineeringinformation engineeringtelecommunicationsradio technologybluetoothengineering and technologyelectrical engineering, electronic engineering, information engineeringinformation engineeringtelecommunicationstelecommunications networksmobile network4Gengineering and technologyelectrical engineering, electronic engineering, information engineeringinformation engineeringtelecommunicationsradio technologyradarengineering and technologyelectrical engineering, electronic engineering, information engineeringinformation engineeringtelecommunicationsmobile phones Palabras clave CMOS Integrated Circuit Radio Frequency RFIC Frequency synthesizer Phase-locked loop (PLL) All-digital phase-locked loop (ADPLL) Digitally-Controlled Oscillator (DCO) Phase Noise Jitter Programa(s) H2020-EU.1.3. - EXCELLENT SCIENCE - Marie Skłodowska-Curie Actions Main Programme H2020-EU.1.3.2. - Nurturing excellence by means of cross-border and cross-sector mobility Tema(s) MSCA-IF-2016 - Individual Fellowships Convocatoria de propuestas H2020-MSCA-IF-2016 Consulte otros proyectos de esta convocatoria Régimen de financiación MSCA-IF - Marie Skłodowska-Curie Individual Fellowships (IF) Coordinador UNIVERSITY COLLEGE DUBLIN, NATIONAL UNIVERSITY OF IRELAND, DUBLIN Aportación neta de la UEn € 175 866,00 Dirección BELFIELD 4 Dublin Irlanda Ver en el mapa Región Ireland Eastern and Midland Dublin Tipo de actividad Higher or Secondary Education Establishments Enlaces Contactar con la organización Opens in new window Sitio web Opens in new window Participación en los programas de I+D de la UE Opens in new window Red de colaboración de HORIZON Opens in new window Coste total € 175 866,00
