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Atm switch for integrated communication, computation and monitoring

Objective

The implementation of a European, single-chip, gigabit ATM switch that is a general-purpose building block for high-performance communication
The development of the architecture of this switch for the efficient support of a broad range of services, both in public, wide and local area networking
The implementation of a gigabit ATM testbed, and the demonstration of gigabit ATM switches integrated and operating inside them
A single-chip 16-by-16 ATM switch at 622 Mbit/s per link (aggregate throughput of 20 Gbit/s)
A serial link transceiver operating at 2.5 Gbit/s
A demonstrator 16-by-16 ATM switch at 622 Mbit/s per link
Upgrade of an existing 155 Mbit/s ATM testbed to 622 Mbit/s
Expected Impact
The successful implementation of the project's objectives will contribute significantly to the enhancement of the competitiveness of the European Telecommunications and Information Systems Industry, since there is no known single chip ATM switch available in the international market. The chip that will be implemented can be used for the development of larger telecommunications ATM switches, capable of handling the huge amounts of data required for the implementation of the information highways. Additionally, it will allow the development of faster and lower-cost local area ATM networks, which, among others, will enable affordable parallel processing using workstation clustering.

Main contributions to the programme objectives:
Main deliverables
A Single Chip ATM switch (ATLAS I) having an aggregate throughput of 20 Gbps and a Serial Link Transceiver capable to handle 2 Gbps of data. A demonstration ATM switch and a relevant ATM testbed was also implemented
Contribution to the programme
Allows the development of faster and lower-cost local area ATM networks.
Technical Approach
The target of the ASICCOM consortium is the design and implementation, by 1998, of a single-chip 8-by-8 ATM switch, with an advanced architecture that supports a broad range of services and with aggregate throughput of at least 40 Gbit/s, and the demonstration of integrated gigabit networking capability with this chip. To achieve this goal, we need to work on the switch architecture, on chip design, on serial link technology, and on testbeds and demonstration.
Single Chip Switch (ATLAS I)
The main innovation of this project is the single-chip nature of the ATM switch. The result of our project will be a switch that integrates on a single chip not only a non-blocking switching fabric, but also significant amounts of buffering, a VC-translation table, an advanced architecture supporting a wide range of services, QoS monitoring circuits at cell level, and basic control and management functions, including appropriate hardware support for the software that monitors failures and implements fault tolerance. It should be emphasised that the design will allow the implementation of the single chip ATM switch in low cost and more dense standard CMOS process.
Switch Architecture
The ATLAS I switch chip will provide a solution in network configurations for both Telecom and high performance computing environments, as well as for demanding multimedia applications. Such environments have to support applications with diverging characteristics ranging from voice (which can afford packet loss to an extent) to multimedia and parallel computation (where data loss may result in prohibitive recovery delays). In order to satisfy the requirements of all such applications, and to reduce overall system cost, the switch features an advanced architecture that includes:
three levels of VC-priority
separate buffer allocation for the three priorities
optional credit-based, multi-lane back-pressure flow control
multicasting support

ATLAS I: Single chip ATM Switch

on-chip support for control / management functions
on-chip VC translation table
on-chip load monitoring for QoS assurance
Switch Demonstrator
In order to prove the usability of the single-chip ATM switch, we will build a demonstrator ATM switch aiming at Broadband Telecommunications. The core of the switch will be the previously described single chip ATM switch. Since HIC/HS is not a very popular standard yet, and also it cannot transmit data in large distances, the interfaces that will be provided are the SDH STM-4-4c (622 Mbit/s). Also, an interface to PCI bus will be implemented, allowing the direct interconnection of computers / workstations to the switch and the demonstration of services over HIC/HS Links.
Serial Link Transceiver
FIBRE CHANNEL Serial Link Transceivers based on Delay Locked Loops (DLLs) will also be implemented. These links will allow 3 Gbaud (2.5 Gbit/s) functioning on a 0.35-micron BiCMOS process and will be also provided as a macrocell, so that it can be integrated in Integrated Circuits.
Testbed Upgrade
Equipment developed in the RACE-I PARASOL project (and later enhanced) will be used to generate and monitor ATM traffic. For simpler functional testing simpler commercial ATM test equipment will be used. This equipment will also be used to generate background traffic to increase the load on the developed switch. The test equipment uses standard interfaces such as TAXI (100 Mbit/s and 140 Mbit/s), SDH (STM-1), parallel and serial pure ATM (155 Mbit/s), PDH34 and DS-links. Also, a HIC/HS interface will also be specified and implemented, allowing the testing of ASICCOM components.

ASICCOM Demonstrator
Standards and Liaison to other ACTS activities
ASICCOM will monitor the ATM standardisation and will contribute to the extension of existing recommendations. The components that will be implemented within the scope of the project will be fully compatible to the related standards. Where standards do not exist yet, we will follow any possibly existing commercial "de facto" standards, or we will try to set new standards.
Also it is participating in the ACTS Concertation Activities, in the Domain 3 and the NIA Chain.
Summary of Trial
The performance, i.e. traffic carrying capability, cell delay and loss statistics, etc., of the switch chip and of larger switches based on it, will be investigated by simulation. Feedback is given to the architecture and design activities, in order to iteratively ensure and improve the high performance of the switch. Similarly, control and management issues of importance for the performance will be investigated by simulation. The load put on the switch will have characteristics close to those found in traffic from real sources, which is important in order to build up confidence in the architecture's performance in a real environment. The work will be carried out by means of network and load simulators. The performance aspects will also be addressed in the testbed. To a certain degree, to validate the correspondence between the properties of the switch design and the demonstrator, the simulation and testbed environment will be kept reasonably consistent. This will also enable a cross validation of simulation and testbed measurement results.
Key Issues
Single Chip, low cost, Gigabit ATM switching for Local and Wide Area Networking
Multilane Back Pressure Flow Control
High Speed serial link Transceivers
Gigabit ATM Testbed

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Funding Scheme

CSC - Cost-sharing contracts

Coordinator

Intracom S.A
EU contribution
No data
Address
19.5 Km Markopoulou Avenue
190 02 Peania
Greece

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Total cost
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Participants (9)

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Last update: 4 May 2023

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Permalink: https://cordis.europa.eu/project/id/AC060

European Union, 2024