Objectif The prime objective of this programme is the improvement in reliability and yield of ultra thin oxide layers used for ULSI CMOS gate and bipolar emitter materials. This objective is in accord with the requirements identified in the Semiconductor Industry Association's road map for the achievement of 0.1 µm transistors. To achieve this prime objective we will improve wafer starting material, ex-situ and in-situ wafer cleaning procedures, and cluster tool dielectric fabrication procedures. We will also improve our understanding of the effect of interface roughness on yield, reliability and tunnel current transport in MOS structures. In support of these objectives we will establish new atomic scale diagnostic techniques of dielectric quality based on scanning probe microscopy methods.The overall result of this programme will be improvements in ultra thin dielectric yield, performance and reliability when the dielectric is used in CMOS technology. The approach taken to achieve the prime objective of the programme is the standard process research and development route of establishing correlations of process and materials parameters with the electrical performance of ultra thin dielectric test structures. Although this is a standard approach, the use of ultra clean processing, cluster tool, and atomic scale diagnostics methods gives the programme a cutting-edge technical approach. Such an approach will be needed to achieve the very demanding SIA road map requirements for reduction of dielectric defect density, thickness uniformity, and reproducibility control.The achievement of the programme objectives will have an impact on the ability to fabricate reliable, ultra thin, ULSI CMOS gate and bipolar emitter structures with high yield. This has been identified by the SIA road map as essential if device dimension of 0.1 µm are to be achieved.As the results of the programme are transferred to advanced production environments the impact of the work will be the strengthening of European IC industry competitiveness. In addition results of the programme will improve the quality of wafers, cluster tools and associated processing regimes. New atomic scale measurement equipment may also be developed from the results of this programme. All of these advances will have an impact on maintaining the competitive edge of the consortiums industrial partners in the world marketplace.The industrial partners to this programme (a major wafer manufacturer and a major process equipment manufacturer) will transfer results of this work to their product base. Since both these industrial partners are major suppliers on a world-wide scale this will be a significant exploitation of the results of this programme. The take up of results of the programme will logically flow to the European semiconductor industry via improved products and processes. Clearly a breakthrough to defect densities in line with the SIA road map targets would have a major impact on CMOS scaling and hence provide significant exploitation opportunities for the European semiconductor industry. Technology transfer is a core activity of the two research organisation partners of the consortium and hence clear exploitation channels are available. Where information dissemination does not prejudice exploitation by the industrial partners information will be presented in the open literature to give maximum exploitation opportunities. Champ scientifique natural sciencesphysical sciencesopticsmicroscopynatural sciencesphysical scienceselectromagnetism and electronicssemiconductivitynatural sciencesmathematicspure mathematicsarithmeticsprime numbers Programme(s) FP4-ESPRIT 4 - Specific research and technological development programme in the field of information technologies, 1994-1998 Thème(s) 4.2 - Reactiveness to Industrial Needs Appel à propositions Data not available Régime de financement CSC - Cost-sharing contracts Coordinateur Aea Technology Contribution de l’UE Aucune donnée Adresse Harwell Laboratory B552 OX11 0RA Didcot Royaume-Uni Voir sur la carte Coût total Aucune donnée Participants (3) Trier par ordre alphabétique Trier par contribution de l’UE Tout développer Tout réduire Advanced Semiconductor Materials Europe Pays-Bas Contribution de l’UE Aucune donnée Adresse Rembrandstlaan 7-9 3723 Bg Bilthoven Voir sur la carte Coût total Aucune donnée Inter University Microelectronics Center Belgique Contribution de l’UE Aucune donnée Adresse Kapeldreef 75 3001 Leuven Voir sur la carte Coût total Aucune donnée Wacker Siltronic Allemagne Contribution de l’UE Aucune donnée Adresse Johannes-Hess Str. 24 84489 Burghausen Voir sur la carte Coût total Aucune donnée
