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Advanced Design, Partitioning and Test in communication subsystems

Ziel

The main objective of ADEPT is to develop, integrate and validate methodologies for the optimal design, partitioning, wafer level assembly and test of communication subsystem modules using Application Specific Integrated Passive (ASIP) devices and Integrated Circuit (ASIC) devices technologies. The project is driven by the end user companies, and with collaborative activities to establish design and CAD, wafer level assembly and test methodologies. The project team includes a company active in high volume cellular mobile communications and another in satellite communications, a company that is a designer and volume manufacturer of high density thin film integrated passive devices and modules, a research institute involved in the R&D of both digital and RF modules and integrated passive devices and a design house with extensive experience in design and test.

Objectives:
With ADEPT, we clearly propose cost effective and time-to-market solutions at the same level of performances than the concept System-On-a-Chip but with minimised risks. This will contribute to level-of-integration decisions, future trends, emerging tools and technologies that may contribute to the development of higher levels of integration. Having adopted a mixed active device technology, high density integrated passive device and module based approach to a specific product requirement the key requirement is then to ensure the optimal use of ingredient technologies in order to achieve the lowest possible cost. This then involves the optimisation of active device selection, the intelligent partitioning of functions between the active and passive media for the specific subsystem architecture adopted, the co-design of the application specific active and passive devices and optimisation of the module manufacturing, assembly and test.

Work description:
The ADEPT project work plan involves a combination of applications focused on partitioning and trade off analysis activities, driven by the end user companies, and collaborative activities to establish design and CAD, wafer level assembly and test methodologies. Highly interactive and interdependent activities to integrate and validate these methodologies using the two applications vehicles will then follow, one about mobile communication in the 5 GHz band and the other about satellite communication in the 30 GHz band.

The project is divided into eight Work Packages (WP) :
- WP 1 is concerned with partitioning and trade off analysis for the specific subsystem architectures of relevance to the two project applications areas. The work completed in this work package will provide the key steering input into the remainder of the project. WP 2, 3 and 4 then provide the enabling methodologies and the tools to allow the benefits of the optimal partitioning approach to be realised;
- WP 2 addresses design, CA and characterisation;
- WP 3 is concerned with wafer level assembly and packaging;
- while WP 4 is focused on ASIP, ASIC and subsystem test;
WP 5 integrates the methodologies and tools from WP2, 3 and 4 and validates them in the implementation of a 5GH WLAN mobile communications and a 30GHz satellite communications module technology vehicle;
WP 6 is responsible for project management, intra-project co-ordination and relationships with other Framework V projects;
- WP 7 is related to the assessment and evaluation of this project;
- WP 8 deals with the dissemination and exploitation of the results of the project.

Wissenschaftliches Gebiet

Programm/Programme

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Finanzierungsplan

CSC - Cost-sharing contracts

Koordinator

ALCATEL SPACE
EU-Beitrag
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Adresse
12 RUE DE LA BAUME
75008 PARIS 08
Frankreich

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Beteiligte (3)

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Letzte Aktualisierung: 13 Juni 2005

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Permalink: https://cordis.europa.eu/project/id/IST-1999-11114/de

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