Obiettivo The latest technology improvements allow the integration of a whole system on a single chip. To support the design of a System-On-a-Chip, Hardware/Software co-design environments have been proposed and are currently being introduced into industrial design flows. Unfortunately, these environments do not provide any support to the designer with respect to testability issues, which are addressed only when the circuit structure is available. New techniques combining ideas from the hardware and software test areas have been recently proposed in order to tackle the test problem early in the design process. The goal of this project is to assess whether these techniques can be successfully extended to co-design environments. If successful, the project will lead to a new generation of co-design environments, where test issues will be taken into account since the very first stages of the design process, thus greatly improving the final product quality while reducing its design cost and time. The latest technology improvements allow the integration of a whole system on a single chip. To support the design of a System-On-a-Chip, Hardware/Software co-design environments have been proposed and are currently being introduced into industrial design flows. Unfortunately, these environments do not provide any support to the designer with respect to testability issues, which are addressed only when the circuit structure is available. New techniques combining ideas from the hardware and software test areas have been recently proposed in order to tackle the test problem early in the design process. The goal of this project is to assess whether these techniques can be successfully extended to co-design environments. If successful, the project will lead to a new generation of co-design environments, where test issues will be taken into account since the very first stages of the design process, thus greatly improving the final product quality while reducing its design cost and time.OBJECTIVESNew techniques from the hardware and software test areas are now available, which are potentially able to tackle the test problem early in the system design cycle.The main objective of the project is to assess whether these new techniques (whose application has up to now been limited to RT-level descriptions) can be suitably extended to provide the designer with some support concerning test issues when a behavioural-level description of the system is available, only. If successful, the project will lead to a new generation of co-design tools able to evaluate different design alternatives not only in terms of performance, area, and power, but also in terms of their testability, i.e. of area and time overhead required to reach a given fault coverage. The nee environments will be able to support the designer in the introduction of suitable Design-for-Testability structures, and in the automatic generation of input stimuli for both manufacturing testing, and design correctness validation.DESCRIPTION OF WORKIn the past years, the introduction of new EDA tools allowed designers to work on higher-level descriptions, leaving the generation of lower-level ones to automatic synthesis tools. Despite this trend, test-related activities are still mainly performed at the gate-level, so that the risk of re-cycling through the design flow due to test problems is high. Recently, several researches proved that testing could be addressed even when the circuit structure is not yet known, and that suitable techniques can be advised to exploit the information existing in a high-level description of a system for evaluating its testability and for reducing the cost for testing in the following design steps. Up to now, these new techniques have been experimented mainly with RT-level descriptions, and very few activities have been performed at the behavioural level. In this project we propose to move a further layer up, and to consider system-level descriptions, i.e. those adopted by Hardware/Software co-design tools to specify the system behaviour. If successful, the project will pave the way for a full research project aimed at devising effective techniques able to support the designer of a SOC system in the adoption of the most suitable test approach and in its implementation. In this way, significant advantages could be achieved in terms of design cost (especially by reducing the time for designing a testable system) and design quality (by identifying the optimal solution in terms not only of area, time, and power constraints, but also of testing).The approach followed in the project will mainly be experimental: we will identify a few benchmark systems whose description is already available in the format required by the POLIS co-design environment, adapt the techniques proposed for RT-level testability evaluation to be used with system-level descriptions, and evaluate their ability to provide useful information about test issues from within the co-design environment. Campo scientifico natural sciencescomputer and information sciencessoftware Programma(i) FP5-IST - Programme for research, technological development and demonstration on a "User-friendly information society, 1998-2002" Argomento(i) 1.1.2.-6.1.1 - FET O: Open domain Invito a presentare proposte Data not available Meccanismo di finanziamento ACM - Preparatory, accompanying and support measures Coordinatore POLITECNICO DI TORINO Contributo UE Nessun dato Indirizzo CORSO DUCA DEGLI ABRUZZI 24 10129 TORINO Italia Mostra sulla mappa Costo totale Nessun dato Partecipanti (1) Classifica in ordine alfabetico Classifica per Contributo UE Espandi tutto Riduci tutto LINKOEPINGS UNIVERSITET Svezia Contributo UE Nessun dato Indirizzo CAMPUS VALLA 581 83 LINKOEPING Mostra sulla mappa Costo totale Nessun dato
