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Device Improved Reliability By Deuterium Annealing

Objetivo

When MOS devices are submitted to electrical stress, electrically active defects called interface traps (Nit) are created at the Si-SiO2 interface. These defects lead to degradation of electrical operating parameters. It has been demonstrated that deuterium annealing greatly reduce the defect generation. The objectives of this project are to assess the benefits of deuterium annealing for different kind of devices and to evaluate its viability as an industrial process, including deuterium recycling. The process will be first studied in an RTP machine and optimised in an industrial furnace. Annealing procedures will be defined for integrated circuits: digital CMOS and NVM. Comparison of products fabricated with conventional hydrogen or deuterium annealing, never used so far, will be performed. At least, a factor 10 improved lifetime is the goal to be achieved.

Convocatoria de propuestas

Data not available

Régimen de financiación

CSC - Cost-sharing contracts

Coordinador

CENTRE COMMUN DE MICROELECTRONIQUE DE CROLLES
Aportación de la UE
Sin datos
Dirección
ZI DU PRE ROUX
38190 CROLLES
Francia

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Coste total
Sin datos

Participantes (5)