Cel The HIDING DIES project aims to develop a highly innovative technology for embedding active chips into high-density printed circuit boards. This 3-dimensional integration will enable a high degree of miniaturization, improved electrical and thermal performance for mobile and communication products. The technological steps are bonding of thin chips (50 µm) on multilayer substrates, embedding of the chips by vacuum lamination of a dielectric layer (RCC), followed by laser drilling of via holes to the chip contacts and to the substrate and finally metallization of vias and conductor lines. For a further increase of functional density integrated passive components can be combined with the chip embedding. The resulting sub-systems with integrated components additionally allow assembly of surface mount devices on the bottom and top surface. All required process steps will be based on existing technologies, however their combination to a cost-effective high-yielding technology require significant scientific and technological research. Besides the process development, a detailed understanding of thermo-mechanical, thermal and electrical performance of such integrated systems has to be achieved. Furthermore development effort has to be made to explore technological limits by handling and bonding very large and very thin chips (50 µm) and by stacking multiple layers with integrated components.The achievement of the development goals will be assessed using two demonstrators, specified by end users. A sensor device combines a surface mounted MEMS chip with embedded control circuits, resulting in an extremely small footprint.The other demonstrator is a power RF application. Target is to create a miniaturized module with excellent electrical and heat conducting properties. With the IC's embedded in the substrate, short connections to filter structures and assembled discrete SMD's at the surface, a compact miniature module can be created. Dziedzina nauki engineering and technologyelectrical engineering, electronic engineering, information engineeringelectronic engineeringsensorsnatural sciencesphysical sciencesopticslaser physics Słowa kluczowe Nanotechnology Risk Assessment Program(-y) FP6-IST - Information Society Technologies: thematic priority under the specific programme "Integrating and strengthening the European research area" (2002-2006). Temat(-y) IST-2002-2.3.1.2 - Micro and nano-systems Zaproszenie do składania wniosków Data not available System finansowania STREP - Specific Targeted Research Project Koordynator TECHNISCHE UNIVERSITAET BERLIN Wkład UE Brak danych Adres Gustav-Meyer-Allee 25 13355 BERLIN Niemcy Zobacz na mapie Koszt całkowity Brak danych Uczestnicy (6) Sortuj alfabetycznie Sortuj według wkładu UE Rozwiń wszystko Zwiń wszystko AT AND S AUSTRIA TECHNOLOGIE AND SYSTEMTECHNIK AKTIENGESELLSCHAFT Austria Wkład UE Brak danych Adres Zobacz na mapie Koszt całkowity Brak danych CHEMNITZER WERKSTOFFMECHANIK GMBH Niemcy Wkład UE Brak danych Adres Zobacz na mapie Koszt całkowity Brak danych DATACON SEMICONDUCTOR EQUIPMENT GMBH Austria Wkład UE Brak danych Adres Zobacz na mapie Koszt całkowity Brak danych INTERUNIVERSITAIR MICRO-ELECTRONICA CENTRUM VZW Belgia Wkład UE Brak danych Adres St-Pieternieuwstraat 41 B-9000 Gent Zobacz na mapie Koszt całkowity Brak danych NOKIA CORPORATION Finlandia Wkład UE Brak danych Adres Zobacz na mapie Koszt całkowity Brak danych PHILIPS ELECTRONICS NEDERLAND B.V. Niderlandy Wkład UE Brak danych Adres Glaslaan 2 5600 MD Eindhoven Zobacz na mapie Koszt całkowity Brak danych
