Objetivo For achieving hardware design correctness, theorem provers such as HOL and Boyer-Moore have been applied for verification. However, in order to construct the correctness proofs, much effort and expertise is required; for nearly every new application new efforts are needed. These methods should only be employed in exceptional cases. High level hardware synthesis techniques are now emerging. The CATHEDRAL design system allows the synthesis of integrated circuits for digital signal processing applications from the high-level behavioural specifications down to the layout. These systems are very complex and integrate a number of techniques, such as data path allocation, scheduling, bus merging, controler synthesis, module generation, layout etc. The costs of design processing iterations due to design bugs is high. Therefore, cross-check ing the results of automatic synthesis is very important. The aim of this Action was to investigate the use of the theorem-proving assistant HOL for proving the correctness of systems synthesised by the CATHEDRAL silicon compilers. Instead of investing the proof effort for each design, the proofs will be made reusable across a whole class of designs. This makes the invested proof effort reusable.The theorem proving assistant higher order logic (HOL) was used for proving the correctness of complex data processing systems that are synthesized by the CATHEDRAL silicon compilers.The following results have been achieved so far:implementation of a general purpose parser generator to support syntactic aspects of embedding SILAGE in HOL;definition of SILAGE semantics in HOL and embedding in the parser generator;definition of a number of correctness preserving transformations based on the formal semantics of SILAGE which have been proven correct;development of a proof methodology for parameterized hardware modules in the CATHEDRAL-II silicon compiler for microcoded digital signal processing (DSP) architectures and application of this methodology for the CATHEDRAL-II ALU;comparison of HOL and Boyer-Moore for the transformational design of parameterized hardware;development of a theory in HOL for finite word length arithmetic, which is essential for correctly dealing with DSP applications such as in CATHEDRALs;development of the signal flow graph (SFG) tracing methodolgy for the automatic verification of lower level implementations (down to switch level transistor circuits as extracted from layout) up to high level SFG algorithmic specifications at the SILAGE level;automatic verification of CATHEDRAL-1 and CATHEDRAL-2 synthesis results for circuits up to 32000 transistors;improvement of the user interface of HOL by means of the CENTAUR system.APPROACH AND METHODS HOL was used to formalise a verification strategy to prove the correctness of the synthesis results. Although synthesis normally assumes correctness by construction, a double check of the results will enhance confidence in the design correctness, and willassist in avoiding costly design iterations due to errors introduced by designers or software tools. To achieve this, appropriate steps in the synthesis trajectory of the CATHEDRAL silicon compilers have been selected for either applying formal design (transformational design) by means of theorem proving in HOL or applying formal verification for increased quality assurances and correctness. In addition to this, feedback was to be given on the use of the HOL system, and further extensions will be made towards its usability for proving hardware correctness. The capabilities and user interface of the HOL system itself were to be improved and extended. PROGRESS AND RESULTS The following results have been achieved up to now: -A general-purpose parser generator has been implemented to support syntactic aspects of embedding SILAGE in HOL. -Definition of SILAGE semantics in HOL and embedding in the parser generator. -Based on the formal semantics of SILAGE a number of correctness preserving transformations have been defined and proven correct. -Development of a proof methodology for parameterised hardware modules in the CATHEDRAL-II silicon compiler for micro-coded DSP architectures. Application of this methodology for the CATHEDRAL-II ALU. -Comparison of HOL and Boyer-Moore for the transformational design of parameterised hardware. -Development of a theory in HOL for finite word length arithmetic, which is essential for correctly dealing with digital signal processing applications such as in CATHEDRALs. -Development of the SFG-Tracing methodology for the automatic verification of lower level implementations (down to switch level transistor circuits as extracted from layout) up to high level signal flow graph algothmic specifications at the SILAGE level. -Automatic verification of CATHEDRAL-1 and CATHEDRAL-2 synthesis results for circuits up to 32,000 transistors (in cooperation with CHARME (3216)). -Improvement of the user interface of HOL by means of the CENTAUR system (INRIA). POTENTIAL The results of this Action will provide progress in methodologies for proving the correctness of synthesis results. The effort required in developing such proofs is distributed and shared by the many design instances that are generated by silicon compilers. This will greatly reduce the effort of proving systems correct and substantially enhance confidence in a design's correctness. New insights have been gained in how to apply and improve the HOL system for verifying correct hardware. Based on the experience with verifying the correctness of generic synthesis steps and design representations, new insights have been gained in how to develop new constructive synthesis methodologies based on theorem-prover concepts. Ámbito científico natural sciencescomputer and information sciencessoftwarenatural sciencesmathematicspure mathematicsarithmeticsagricultural sciencesagriculture, forestry, and fisheriesagricultureindustrial cropsfoddernatural scienceschemical sciencesinorganic chemistrymetalloidsnatural sciencescomputer and information sciencesdata sciencedata processing Programa(s) FP2-ESPRIT 2 - European strategic programme (EEC) for research and development in information technologies (ESPRIT), 1987-1992 Tema(s) Data not available Convocatoria de propuestas Data not available Régimen de financiación Data not available Coordinador INTERUNIVERSITAIR MIKROELEKTRONICA CENTRUM Aportación de la UE Sin datos Dirección KAPELDREEF, 75 3030 HEVERLEE Bélgica Ver en el mapa Coste total Sin datos Participantes (2) Ordenar alfabéticamente Ordenar por aportación de la UE Ampliar todo Contraer todo NEDERLANDSE PHILIPS BEDRIJVEN BV Países Bajos Aportación de la UE Sin datos Dirección PROF. HOLSTLAAN, 4 5656 AA EINDHOVEN Ver en el mapa Coste total Sin datos University of Cambridge Reino Unido Aportación de la UE Sin datos Dirección New Museums Site Pembroke Street CB2 3QG Cambridge Ver en el mapa Coste total Sin datos
