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Novel Parallel Algorithms for New Real-Time VLSI Architectures

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The NANA Action aimed to develop new parallel real-time VLSI architectures for a large variety of applications, such as image and seismic processing, robotics, video, telecommunications, factory automation, biomedical technology and adaptive beam forming.The most important classes of techniques needed in these domains are algebraic and numerical techniques for multidimensional problems and their application as subsystems in other algorithms.
To allow for the future design of high-complexity applications in mega-chip technologies, synthesis techniques starting from very high-level behavioural descriptions are crucial. Research includes the exploration of novel methodologies in this area. Efforts pursued in NANA2 (6632) also include part of the implementation in software tools.
Novel very large scale integration (VLSI) architectures and parallel algorithms were developed for multidimensional signal processing (MDSP), which is used in image processing, graphics and system control. These algorithms and architectures are needed in real-time systems and will have a beneficial impact on computer-aided hardware design and synthesis environments. Novel parallel algorithmic kernels were investigated. In particular, effort was spent on parallel algorithms for linear algebra system solvers and path problems, adaptive signal processing and adaptive control applications such as beam forming and parameter estimation, and large scale modelling of partial differential equations, all leading to more efficient systolic and single instruction multiple data (SIMD) realizations. In addition, graphics processing related kernel-like efficient radiosity derivation, 3-dimensional image reconstruction, segmentation and visualization have been tackled. New parallel architectural styles and methodologies have been investigated. Work concentrated on: efficient control/data flow models and algorithmic transformations for realizing the multi-dimentional data in both regular and irregular real-time signal processing algorithms in an effective way on memory organisations; semantics-preserving transformative methods for systolic arrays with emphasis on global operation and semi-systolic or piecewise regular architectures; and an extended data model and clustering/partitioning methods for array synthesis.
APPROACH AND METHODS
The work has been divided into two areas:
1.Novel Parallel Algorithms. Past experience has demonstrated that putting effort into the algorithm is essential for the success of a design, as most classical algorithms are implicitly tailored to sequential processing. For this reason a number of repr esentative algorithms in the domain of MDSP will be analysed in order to develop different, more parallel, algorithms.
2.Architectural Methodologies. Classical solutions, such as general-purpose standard machines, are too wasteful in terms of area-cost and power dissipation for a given throughput. Moreover, the communication and memory size bottlenecks are not removed. I n order to alleviate these shortcomings, fundamental breakthroughs are needed in novel algorithm development and high-level application- or domain-specific VLSI components. To achieve this, efficient target architectural styles have been defined, including regular arrays and application-specific data-flow dominated processors. The emphasis in NANA 2 lies on the architectural methodologies and the environment to synthesise such parallel architectures from high level behavioural descriptions are investigated.
PROGRESS AND RESULTS
Results have been produced in terms of novel parallel algorithms and architecture methodologies and their impact on synthesis strategies and environments which are efficient in terms of chip-area and off-chip memory and which comply with the throughput, power and pin-count limitations of VLSI based realisations.
The main focus of the Action in the first work area has been the investigation of novel parallel algorithmic kernels. In particular, effort has been spent recently on parallel algorithms for linear algebra system solvers and path problems, adaptive signalprocessing and adaptive control applications such as beamforming and parameter estimation, and large scale modeling of Partial Differential Equations, all leading to more efficient systolic and SIMD realisations. In addition, graphics processing relatedkernel like efficient radiosity derivation, 3D image reconstruction, segmentation and visualization have been tackled.
In the second area of work, new parallel architectural styles and methodologies have been investigated for application to the type of problems addressed in the first work-package. Work concentrated on: efficient control/data flow models and algorithmic transformations for realizing the multi-dimensional data in both regular and irregular real-time signal processing algorithms in an effective way on memory organisations; semantics preserving transformative methods for systolic arrays with emphasis on global operation and semi-systolic or piece-wise regular architectures; and an extended data model and clustering/partitioning methods for array synthesis.
In addition, a considerable cooperative effort has been put into holding common workshops in order to discuss information from work at the partner sites in order to arrive at the 19 common deliverables which have been produced at the end of NANA. New workshops are planned in the context of NANA2 (6632).
POTENTIAL
This work is of major importance for the development of efficient systems in many fields of applied information technology, such as image or sonar processing, robotics, video, telecommunications, advanced process control and adaptive beam forming.
Studying the systems in terms of both novel parallel algorithms and efficient new architectural methodologies will allow them to be mapped onto future VLSI realisations with a smaller design and production cost.

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INTERUNIVERSITAIR MIKROELEKTRONICA CENTRUM
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Letzte Aktualisierung: 19 August 1994

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Permalink: https://cordis.europa.eu/project/id/3280/de

European Union, 2024