Objective The objective of the HYETI project was to develop the design methodology, design tools and architecture necessary to achieve high yields on ULSI (Ultra Large Scale Integration) and WSI (Wafer Scale Integration) integrated circuits. The yield models, specialised architectures and focused CAD tools required for reconfiguration at the end of manufacture were to be studied in this project. Because defect densities in modern process technology are such that working wafer scale circuits can only be manufacturedby introducing redundancy into a chip, enabling the defects to be avoided by reconfiguration during production, this work was of high value. The need to produce a demonstrator to focus the many multi-discipline, interrelated facets of the WSI design problem was an important consideration from the start of the project. The objective of the project was to develop the design methodology, design tools and architecture necessary to achieve high yields on ultra large scale integration (ULSI) and wafer scale integration (WSI) integrated circuits. The yield models, specialised architectures and focused computer aided design (CAD) tools required for reconfiguration at the end of manufacture were to be studied in this project.As a conclusion to the work on yield analyses, the project found that the most satisfactory way to handle yield prediction for a specific topology is by graphic simulation. 2 architectures were selected for WSI implementation after a wide investigation: a 2-dimensional fast Fourier transform (FFT) processor and a processor array. After extensive investigation, the decision was taken during this preproject study to design and manufacture, in the follow up project, a 4 Mbit static random access memory (RAM), a systolic array and a reconfigurable 16-bit microprocessor.As a conclusion to the work on yield analyses, the project found that the most satisfactory way to handle yield prediction for a specific topology is by graphic simulation. Two architectures were selected for WSI implementation after a wide investigation: a 2-D Fast Fourier Transform (FFT) processor, and a processor array. After extensive investigation, the decision was taken during this pre-project study to design and manufacture, in the follow-up project, a 4 Mbit static RAM, a systolic array and a reconfigurable 16-bit microprocessor. As this was just a one-year pre-project to investigate the feasibility of WSI, only limited results were achieved. The work, with an adjusted workplan and modification in the partnership, has been continued under project 824. Fields of science engineering and technologyelectrical engineering, electronic engineering, information engineeringelectronic engineeringcomputer hardwarecomputer processorsnatural sciencesmathematicspure mathematicstopology Programme(s) FP1-ESPRIT 1 - European programme (EEC) for research and development in information technologies (ESPRIT), 1984-1988 Topic(s) Data not available Call for proposal Data not available Funding Scheme Data not available Coordinator SGS Thomson Microelectronics SA EU contribution No data Address 17 avenue des Martyrs 38340 Grenoble France See on map Total cost No data Participants (8) Sort alphabetically Sort by EU Contribution Expand all Collapse all BULL SA France EU contribution No data Address AVENUE DE MALAKOFF 75116 PARIS See on map Total cost No data British Telecom plc (BT) United Kingdom EU contribution No data Address British Telecom Laboratories Martlesham Heath IP5 7RE Ipswich See on map Total cost No data Brunel University United Kingdom EU contribution No data Address UB8 3PH Uxbridge See on map Total cost No data Cirrus Computer Ltd United Kingdom EU contribution No data Address 29-30 High Street PO16 7AD Fareham See on map Total cost No data Commissariat à l'Energie Atomique (CEA) France EU contribution No data Address Centre d'Études de Grenoble 17 avenue des Martyrs 38041 Grenoble See on map Total cost No data Institut National Polytechnique de Grenoble France EU contribution No data Address 38402 Saint-Martin-d'Hères See on map Total cost No data Institut National Polytechnique de Grenoble France EU contribution No data Address 46 avenue Félix Viallet 38031 Grenoble See on map Total cost No data Technische Hochschule Darmstadt Germany EU contribution No data Address Schloßgartenstraße 64289 Darmstadt See on map Total cost No data
