Objectif
The objective of project 958 was to exploit the potential advantages of high-density structures on which VLSI chips could be connected with very dense (100 to 125micron pitch) TAB (Tape Automated Bonding) interconnections on a high-performance multichipsubstrate. The project was complementary to project number830 as part of the "Advanced Packaging" workprogramme.
The objective of project 958 was to exploit the potential advantages of high density structures on which very large scale integration (VLSI) chips could be connected with very dense (100 to 125 micron pitch) tape automated bonding (TAB) interconnections on a high performance multichip substrate.
2 TAB technologies were developed:
bumped chip TAB;
bumped tape TAB (BTAB).
Bumped chip requires additional wafer processing, while bumped tape requires an additional photolithography stage for the tape.
Manufacturing processes were adjusted to reach the level of fully controlled product at 125 micron pitch. At 100 micron, good results were achieved, but at laboratory level.
The high density substrate development was concentrated on the fabrication of multilayer structures with track pitches as small as 125 micron in order to enable the pitches on the chips and on the substrate to be identical, hence maxmising the interconnection density. Under these conditions, the via hole diameters needed to be 50 micron or less. This was beyond the limits of mechanical drilling, so laser drilling techniques were developed.
Liquid immersion in fluorocarbon was chosen to extract heat from the rear surface of the chips.
In order to bring together the various developments in the hardware and design techniques, 2 demonstrators were realised.
Electrical and thermal performance measurements have shown that such structures can be used as a basic building block of a very high performance system (1 GHz clock or 20-50 ns system cycle time).
Two TAB technologies were developed: bumped chip TAB and bumped tape TAB (BTAB). Bumped chip requires additional wafer processing, while bumped tape requires an additional photolithography stage for the tape.
Manufacturing processes were adjusted to reach the level of fully controlled product at 125micron pitch. At 100micron, good results were achieved, but at laboratory level.
The high-density substrate development was concentrated on the fabrication of multilayer structures with track pitches as small as 125micron in order to enable the pitches on the chips and on the substrate to be identical, hence maximising the interconne ction density. Under these conditions, the viahole diameters needed to be 50micron or less. This was beyond the limits of mechanical drilling, so laser drilling techniques were developed.
Liquid immersion in fluorocarbon was chosen to extract heat from the rear surface of the chips. Thermal trials corroborated the thermal modelling work, which indicated that power densities up to more than 20 W/cm2 can be effectively dealt with by this means.
In order to bring together the various developments in the hardware and design techniques, two demonstrators were realised. The first is an array of 36ICs, each 100mm2 with 284I/Os on 125micron pitch, mounted by TAB onto a multilayer substrate of 100cm2 having tracks at 125micron pitch and 50micron laser-drilled viaholes. The ratio of silicon area to substrate area is extremely high(36%).
The second demonstrator incorporates a high speed multiplexer circuit, using ECL ICs designed and made by British Telecom with TAB pitches of 162 and 200micron. There are also ten of the same chips (125micron pitch), as on the first demonstrator, whichwill enable testing under conditions of high total power dissipation. Additional surface-mounted resistors and capacitors are reflowsoldered onto both sides of the substrate. The multiplexer circuit has been connected to a demultiplexer built in conventional technology and compared to a conventionally built multiplexer. Electrical and thermal performance measurements have shown that such a structure can be used as a basic building-block of a very high performance system (1 GHz clock or 2050ns system cycle time).
The main application areas for the TAB technology within the telecommunication and industrial segments are for high-speed switches and processors, display drivers and high-speed transmission systems. TAB offers a packaging technique allowing the assembly of VLSI chips in compact modules where electrical signals are closely monitored and heat can be efficiently evacuated.
Exploitation
The know-how on TAB generated in the project has been made available to the sub-contractor MCTS (a French tape manufacturer) in order to commercialise complex TAB tapes (200 to 300 I/Os, with pitch down to 125 microns).
Champ scientifique
Programme(s)
Thème(s)
Data not availableAppel à propositions
Data not availableRégime de financement
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78340 Les-Clayes-Sous-Bois
France