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Knowledge-Based Design Assistant for Modular VLSI Design

Objective

The objective of project 1058 was the production of an interactive knowledge-based system for the verification of the electrical, functional and timing correctness of flexible VLSI modules as generated by silicon compilers. This was achieved in the two major work-packages of the project.
An integrated working environment in a workstation is being developed that can support both the design of very large scale integration (VLSI) circuits and the production process, as well as the optimal preparation of tests of the product itself, including failure diagnostics.

The objective was the production of an interactive knowledge based system for the verification of the electrical, functional and timing correctness of flexible very large scale integration (VLSI) modules as generated by silicon compilers. An interactive and open system architecture was developed based on the concept of structure procedural interface (SPI), which allows direct and interactive communication between intelligent verification tools and a VLSI design tool. The system architecture enables interactive communication among computer aided design (CAD) tools operating in parallel. A prototype system where intelligent verification tools (electrical verification, rule based verification, timing verification, simulation) are integrated with schematics, symbolic and module generator editors in a bidirectional way has been realized. Intelligent application tools were built using knowledge based concepts. They allow for timing, electrical and hierarchical correctness verification by analysis and intelligent simulation. in the accurate timing verification program, novel solutions for the false path problem were worked out and demonstrated. Hierarchical timing verification and view generation algorithms suitable for false path avoidance were developed and implemented. A formal metal oride semiconductor (MOS) VLSI circuit theory was developed and implemented in the program. It provides the metaknowledge required for more general applicability of the rule based expert verification system. In addition, the expert system is capable of verifying complete chip designs by a total reconstruction of design hierarchy based on flat layout extraction. This is a major breakthrough in verification technology. Major achievements on circuit simulation acceleration were obtained by exploiting a new explicit event oriented integration scheme and by exploiting parallelism on multiprocessors. An intelligent extractor with a data reduction filter provides the link to symbolic or procedural module layout generators.
In the first work-package an interactive and open system architecture was developed based on the concept of SPI (Structure Procedural Interface), which allows direct and interactive communication between intelligent verification tools and a VLSI design tool. The system architecture enables interactive communication among CAD tools operating in parallel. A prototype system where intelligent verification tools (electrical verification, rule based verification, timing verification, simulation) are integratedwith schematics, symbolic and module generator editors in a bidirectional way has been realised.
SPI has been released in the public domain. In this way, SPI is a potential candidate for becoming a standard for communication between electronic CAD tools in as far as structure information is concerned. Its acceptance in the CAD community will make the interchange of interactive tools much easier. Presentations on SPI were given at the 1989 ESPRIT Conference as well as the ECIP-II seminar (European CAD Integration Project) in November 1989. A presentation and demonstration of SPI was also made at the E DAC conference in Glasgow in March 1990.
Contacts have been established with the CFI Initiative with respect to SPI. SPI was presented to the CFI committee in Philips, Eindhoven in October 1989, and will be used as a major demonstrator for interactive CAD tool integration within CFI. It was alsopresented and demonstrated within the CFI initiative during the ACM/IEEE Design Automation Conference in Las Vegas in 1990.
EDC (European Design Centre), a research and development organisation located in Leuven, Belgium (jointly owned by Mentor Graphics, Philips International BV and IMEC), worked out a licence arrangement for making SPI and its prototype support tools available in the public domain. In this way it is hoped to circumvent barriers for getting the concepts accepted in other places.
In the second work-package, intelligent application tools were built using knowledge-based concepts. They allow for timing, electrical and hierarchical correctness verification by analysis and intelligent simulation. In the accurate timing verification program, novel solutions for the false path problem were worked out and demonstrated. Hierarchical timing verification and view generation algorithms suitable for false path avoidance were developed and implemented. A formal MOS VLSI circuit theory was deve loped and implemented in the DIALOG program. It provides the meta-knowledge required for more general applicability of the rule-based expert verification system. In addition, the VERA expert system is capable of verifying complete chip designs by a total reconstruction of design hierarchy based on flat layout extraction. This is a major breakthrough in verification technology.
Major achievements on circuit simulation acceleration were obtained by exploiting a new explicit event-oriented integration scheme and by exploiting parallelism on multi-processors. An intelligent extractor with a data reduction filter provides the link to symbolic or procedural module layout generators.
The major achievements of the project in its final phase were:
-Extensive documentation of the results achieved in parallel algorithms for wave-form relaxation-based circuit simulation.
-Application of SLOCOP-II to a broader range of examples coming from CATHEDRAL-II. This was done in cooperation with Philips Components (UK). Comparisons and improvements of the accuracy of the delay estimations in SLOCOP-II with respect to circuit simul ation were also carried out. SLOCOP-II is being used by circuit designers for the timing verification of combinatorial modules in CATHEDRAL-II, and a manual of the SLOCOP-II program has been written.
-Production of a DIALOG program manual.
-Breakthrough by VERA in the hierarchical verification of complete chips starting from flat layout extraction.
-Further integration of CAD tools via the SPI interface. The following tools have been coupled up till now: SLOCOP, DIALOG, VERA, CINNAMON, CSWAN, CASS, CAMELEON and MGE. Two tools not within this project have also been coupled: HILARICS, a structure des cription language, and LOGMOS, a register transfer level simulator.
-Efforts have been made to promote SPI at the EDAC Conference (during the organisation of the final workshop in January 1990), and through the ECIP and CFI channels.

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Coordinator

IMEC VZW
EU contribution
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Address
KAPELDREEF
3030 HEVERLEE
Belgium

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Participants (3)