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Real-Time DSP Emulation System

Ziel

The objective of RETIDES is to provide a platform for the fast prototyping of digital signal processing (DSP) systems. To this end, techniques, hardware and software will be provided to compile DSP algorithms, described in a high-level language, onto programmable parallel hardware for real-time execution.
A platform has been developed for the fast prototyping of digital signal processing (DSP) systems. To this end, techniques, hardware and software have been provided to compile DSP algorithms, described in a high level language, onto programmable parallel hardware for real time execution.

The DSP emulation platform resulting from this work is a turn key integrated hardware and software computer aided design (CAD) tool. It plays a crucial role in the design flow of integrated DSP systems, leading to:
the ability to verify DSP systems in their real time environment before committing them to silicon integration, so lessening design risks;
a large reduction in simulation time and prototyping effort, resulting in shorter development cycles;
the ability to develop hardware and software in parallel;
the ability to prototype in the early phases of a design project (behavioural emulation) as well as in the end phase (hardware emulation);
the provision of a significant acceleration in simulations when used in a simulation mode (with tracing of signals, etc).

A full specification of the DSP real time emulation system has been achieved. A first product resulting from the project has hit the market. In June 1993, Integrated Circuit Applications (INCA) released their new 'Virtual ASIC II' logic emulation system with introduction at the Design Automation Conference, DAC '93.
The DSP emulation platform resulting from this work will be a turn-key integrated hardware and software CAD tool. It will play a crucial role in the design flow of integrated DSP systems, leading to:

- the ability to verify DSP systems in their real-time environment before committing them to silicon integration, so lessening design risks
- a large reduction in simulation time and prototyping effort, resulting in shorter development cycles
- the ability to develop hardware and software in parallel
- the ability to prototype in the early phases of a design project (behavioural emulation) as well as in the end phase (hardware emulation)
- the provision of a significant acceleration in simulations when used in a simulation mode (with tracing of signals, etc).

RETIDES exploits results from project 97 and from SPRITE (project 2260), which resulted in the CATHEDRAL and PIRAMID silicon compilers for DSP ASICs, currently undergoing commercialisation as MISTRAL compilers in the DSP Station developed at EDC/Mentor.

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PHILIPS INTERNATIONAL TECHNOLOGY CENTRE LEUVEN
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Letzte Aktualisierung: 17 Juni 1994

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Permalink: https://cordis.europa.eu/project/id/6800/de

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