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Performance-Critical Applications of Parallel Architectures

Objetivo

Performance-critical applications typically involve manipulation of large, sparse discrete data objects. One of the major causes of low performance for these applications is the hardware memory organisation in present-day high-performance computers. Progress towards the general applicability of high-performance computing depends upon the removal of this memory performance barrier for the class of sparse computations. Hence sparse computations and hardware memory architecture form the main technical themes of the APPARC project.
High performance computing (HPC) is a critical technology for future economic growth. Technical progress in HPC has been rapid only in a few application areas. Unfortunately, a large and important class of applications is not yet amenable to high performance execution, due to a mismatch with currently available techniques at all levels of the computational problem solving process. This class of computations can be referred to as performance critical applications. It requires a concerted interdisciplinary research effort to break this barrier.

Some of the major achievements so far are:
the definition of cache performance models which are specifically targeted for sparse computations and do not rely on simulations;
a comprehensive analysis of data locality optimizations for optimizing compilers;
the design of special hardware support to enable out of order memory accesses which relieve memory conflicts;
a preliminary definition of a level of abstraction for sparse computations, which enables compiler optimizations to be performed for sparse computations.
APPROACH AND METHODS

The development of computational solutions to performance-critical applications embraces many different levels of abstraction, from mathematical modelling of the application, through algorithm and software development, to hardware implementation. Thus tackling the two project themes is no simple matter: the interaction between the applications and the memory architecture affects all levels of the problem-solving process. Consequently APPARC studies the two themes across eight interrelated enabling areas: performance-critical applications, parallel algorithms, problem-solving environments, performance modelling and evaluation, high-level languages, compiler design, operating systems, and hardware architecture.

POTENTIAL

The research groups involved in the APPARC proposal have considerable expertise, spanning all eight enabling areas. They also have strong links with leading research groups elsewhere in Europe and around the world. They are committed to collaboration in the interdisciplinary mode that will be necessary for APPARC research to succeed, and an extensive programme of workshops and exchange of personnel is planned. The APPARC group intends to interact strongly with the industrial community by firstly gathering information on the real computing challenges that industry is facing, and secondly, by disseminating research results to high-performance computer manufacturers and users via summer schools, advanced training courses and on-site visits.

Tema(s)

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Convocatoria de propuestas

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Régimen de financiación

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Coordinador

RIJKS UNIVERSITEIT LEIDEN
Aportación de la UE
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Dirección
NIELS BOHRWEG 1, 9512
2333 CA/ 2 LEIDEN
Países Bajos

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Participantes (8)