Community Research and Development Information Service - CORDIS

FP7 REFLECT

REFLECT

Project reference: 248976
Funded under: FP7-ICT

Rendering FPGAs to Multi-Core Embedded Computing [Print to PDF] [Print to RTF]

From 2010-01-01 to 2012-12-31

Project details

Total cost:

EUR 3 703 578

EU contribution:

EUR 2 719 999

Coordinated in:

Czech Republic

Call for proposal:

FP7-ICT-2009-4

Funding scheme:

CP - Collaborative project (generic)

To develop an approach and a tool-chain to improve productivity by accelerating development cycles of reconfigurable systems by more than two orders of magnitude

The ever increasing need for additional product functionalities, safety, and security, drives many product suppliers towards the need for more and more platform performance. For instance, next-generation UAVs (unmanned aerial vehicles) are expected to be much more complex in terms of sensing. As such, the analysis and decision-making processes will lead to a higher performance requirement, together with the need of low cost solutions. Another example is audio encoding, where better performance and improved encoding quality are features of major interest. While these requirements are met by implementing as many functions as possible in hardware it is certainly desirable to host product functionalities on as few hardware platforms as possible in order to reduce size, weight and power of products.
Reconfiguration has been recognized as a key technique to achieve these goals. However, designing reconfigurable systems is an extremely cumbersome and error-prone process. As a result, the potential of reconfiguration is only achieved at high design effort and cost.
REFLECT aims at developing an approach and a tool-chain to improve productivity by accelerating development cycles of reconfigurable systems by more than two orders of magnitude.

Objective

The relentless increase in capacity of Field-Programmable Gate-Arrays (FPGAs) makes them vehicles of choice for both prototypes and final products requiring on-chip multi-core, heterogeneous and reconfigurable systems. Multiple cores can be embedded as hard- or soft-macros, have customizable instruction sets, multiple distributed RAMs and/or configurable interconnections. Their flexibility allows them to achieve orders of magnitude better performance than conventional computing systems via customization. Programming these systems, however, is extremely cumbersome and error-prone and as a result their true potential is only achieved at an unreasonably high effort.\nThis project will develop, implement and evaluate a novel compilation and synthesis system approach for FPGA-based platforms. We rely on Aspect-Oriented (AO) Specifications to covey critical domain knowledge to a mapping engine while preserving the advantages of a high-level imperative programming paradigm in early software development and portability. We leverage AO specifications and a set of transformations to generate an intermediate representation using an extensible mapping language (LARA). LARA specifications will allow the exploration of alternative architectures and run-time adaptive strategies enabling the generation of flexible hardware cores that can be easily incorporated into larger multi-core designs. We will evaluate the effectiveness of the proposed approach using partner-provided codes from the domain of audio/video processing and real-time avionics.\nWe expect the technology developed here to be integrated by our industrial partners, a leading compilation tool supplier for reconfigurable systems and a worldwide solution supplier of embedded high-performance systems. The academic partners will promote human resources with technical excellence in the area of architectures and software development thus enabling the sustainability of a vibrant information technology European fabric.

Related information

Open Access

Coordinator contact

Zlatko Petrov, (Sr. Advanced Research Scientist)
Tel.: +33 489 122 097
Fax: +420 532 115 008
E-mail

Coordinator

HONEYWELL INTERNATIONAL SRO
Czech Republic
Holandská 2/4
Brno, Czech Republic
Administrative contact: Jan Kubalcík
Tel.: +420 532 115 512
Fax: +420 532 115 001
E-mail

Participants

Karlsruher Institut fuer Technologie
Germany
Kaiserstrasse
Karlsruhe, Germany
Administrative contact: Jens Becker
Tel.: +497216086498
Fax: +497216082925
E-mail
ACE ASSOCIATED COMPILER EXPERTS B.V.
Netherlands
DE RUYTERKADE 113
AMSTERDAM, Netherlands
Administrative contact: Marius Schoorel
Tel.: +31 20 6646416
E-mail
TECHNISCHE UNIVERSITEIT DELFT
Netherlands
Stevinweg
DELFT, Netherlands
Administrative contact: Dennis F. Van Doorn
Tel.: +31 15 2789344
Fax: +31 15 2781543
E-mail
UNIVERSIDADE DO PORTO
Portugal
PRACA GOMES TEIXEIRA
PORTO, Portugal
Administrative contact: Joao Cardoso
Tel.: +351 916629046
Fax: +351 22 557 4103
E-mail
INESC ID - INSTITUTO DE ENGENHARIA DE SISTEMAS E COMPUTADORES, INVESTIGACAO E DESENVOLVIMENTO EM LISBOA
Portugal
Rua Alves Redol
LISBOA, Portugal
Administrative contact: Pedro Diniz
Tel.: +351 214 233 517
Fax: +351 214 233 252
E-mail
Coreworks - Projectos de Circuitos e Sistemas Electronicos S.A.
Portugal
Rua Dona Estefania
Lisboa, Portugal
Administrative contact: Fernando Gonçalves
Tel.: +351 213 100 213
Fax: +351 213 546 061
E-mail
IMPERIAL COLLEGE OF SCIENCE, TECHNOLOGY AND MEDICINE
United Kingdom
Exhibition Road, South Kensington Campus
LONDON, United Kingdom
Administrative contact: Shaun Power
Tel.: +44 207 594 8773
Fax: +44 207 594 8609
E-mail
HONEYWELL EOOD
Bulgaria
BUL HRISTOFOR COLUMB
SOFIA, Bulgaria
Administrative contact: Zlatko Petrov
Tel.: +33489122097
E-mail
Record Number: 93845 / Last updated on: 2014-10-06