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SQWIRE

Project reference: 257111
Funded under: FP7-ICT

Silicon Quantum Wire Transistors [Print to PDF] [Print to RTF]

From 2010-09-01 to 2013-08-31

Project details

Total cost:

EUR 4 326 034

EU contribution:

EUR 3 150 000

Coordinated in:

Ireland

Call for proposal:

FP7-ICT-2009-5

Funding scheme:

CP - Collaborative project (generic)

SQWIRE develops industry compatible CMOS technology based on novel Si nanowire transistor structures.

The aim of the SQWIRE project is to develop a disruptive, industry-compatible CMOS technology based on novel silicon nanowire transistor structures. As has been demonstrated both theoretically and experimentally, nanowire MOS transistors can be fabricated at wafer level using silicon-on-insulator (SOI) substrates and these novel devices have shown electrical properties that are comparable or even superior to those of regular transistors. Two such novel devices are the Gated Resistor (a junctionless transistor simulated, prototype fabricated and patented) and the variable-barrier tunnel transistor (VBT, simulated and patented). To obtain industrial validation, fabrication routes will be developed for these devices on novel 300 mm SOI wafers with silicon film thicknesses of only 10 nm. These routes will be underpinned by process development targeting atom-scale control of the silicon film thickness across the wafer. Device performance will be characterised at die-level and evaluated in a statistically meaningful manner at wafer level. The extracted parameters will serve as the basis for the development of a compact model of the Gated Resistor devices, which can be used for further circuit design and the validation of advanced numerical simulations. The fabrication process for the first device (Gated Resistor) is less complex and more flexible than that of regular transistors. It has the potential of increasing yield and reducing the price of integrated circuits. Furthermore, the Gated Resistor offers the promise of superior scaling to sub-22 nm dimensions compared to regular transistors. In addition, the process can easily be implemented in semiconductor materials other than silicon. The second device (Variable Barrier Transistor) is capable of providing subthreshold slopes sharper than any conventional transistor. This permits one to reduce the supply voltage of integrated circuits, and hence their energy consumption.

Objective

The aim of the SQWIRE project is to develop a disruptive, industry-compatible CMOS technology based on novel silicon nanowire transistor structures. The co-ordinator has demonstrated both theoretically and experimentally that nanowire MOS transistors can be fabricated at wafer level using silicon-on-insulator (SOI) substrates. These novel devices have shown electrical properties that are comparable or even superior to those of regular transistors.\nTwo such novel devices are the Gated Resistor (a junctionless transistor simulated, prototype fabricated and patented) and the variable-barrier tunnel transistor (VBT, simulated and patented). To obtain industrial validation, fabrication routes will be developed for these devices on novel 300 mm SOI wafers with silicon film thicknesses of only 10 nm. These routes will be underpinned by process development targeting atom-scale control of the silicon film thickness across the wafer.\nDevice performance will be characterised at die-level and evaluated in a statistically meaningful manner at wafer level. The extracted parameters will serve as the basis for the development of a compact model of the Gated Resistor devices, which can be used for further circuit design and the validation of advanced numerical simulations.\nThe fabrication process for the first device (Gated Resistor) is less complex and more flexible than that of regular transistors. It has the potential of increasing yield and reducing the price of integrated circuits. Furthermore, the Gated Resistor offers the promise of superior scaling to sub-22 nm dimensions compared to regular transistors. In addition, the process can easily be implemented in semiconductor materials other than silicon. The second device (Variable Barrier Transistor) is capable of providing subthreshold slopes sharper than any conventional transistor. This permits one to reduce the supply voltage of integrated circuits, and hence their energy consumption.

Related information

Coordinator

UNIVERSITY COLLEGE CORK, NATIONAL UNIVERSITY OF IRELAND, CORK
Ireland
Lee Maltings, Prospect Row
Cork, Ireland
Administrative contact: Conor Delaney
Tel.: +353 21 490 4263
Fax: +353 21 4904058
E-mail

Participants

INTERUNIVERSITAIR MICRO-ELECTRONICA CENTRUM VZW
Belgium
Kapeldreef
LEUVEN, Belgium
Administrative contact: Christine Van Houtven
Tel.: +3216281613
Fax: +3216281812
E-mail
MAGWEL NV
Belgium
MARTELARENPLEIN
LEUVEN, Belgium
Administrative contact: Bart De Smedt
Tel.: +32 16 46 86 88
Fax: +32 16 46 86 89
E-mail
UNIVERSITAT ROVIRA I VIRGILI
Spain
CARRER DE L'ESCORXADOR
TARRAGONA, Spain
Administrative contact: Rosa Solà Alberich
Tel.: +34 977559522
Fax: +34 977558278
E-mail
COMMISSARIAT A L ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
France
RUE LEBLANC
PARIS 15, France
Administrative contact: Marie-Laure Page
Tel.: +33 4 38782396
Fax: +33 4 38785183
E-mail
S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES SA
France
CHEMIN DES FRANQUES - PARC TECHNOLOGIQUE DES FONTAINES
BERNIN, France
Administrative contact: Nelly Kernevez
Tel.: +33 4 76 92 96 23
Fax: +33 4 76 92 94 31
E-mail
INSTITUT POLYTECHNIQUE DE GRENOBLE
France
AVENUE FELIX VIALLET
GRENOBLE CEDEX 1, France
Administrative contact: Valerie Miscioscia
Tel.: +33456529505
Fax: +33456529501
E-mail
INTEL PERFORMANCE LEARNING SOLUTIONS LIMITED
Ireland
Collinstown Industrial Park
LEIXLIP, CO KILDARE, Ireland
Administrative contact: Bernard Capraro
Tel.: +353 1 606 4228
Fax: +353 1 606 4210
E-mail
CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE
France
Rue Michel -Ange
PARIS, France
Administrative contact: N/A N/A
Tel.: +00 0 000000
E-mail
UNIVERSITE JOSEPH FOURIER GRENOBLE 1
France
Avenue Centrale, Domaine Universitaire
GRENOBLE, France
Administrative contact: N/A N/A
Tel.: +00 0 000000
E-mail
Record Number: 95564 / Last updated on: 2014-10-06