Final Report - ESL_STR (Automatic hardware generation using the stream programming paradigm)
Project ID: 223819Funded under: FP7-PEOPLE
This is the final publishable summary report for the ESL_STR project. Funded under the European Commission (EC)'s Seventh Framework Programme (FP7), ESL_STR produced an end-to-end Computer-aided design (CAD) tool that utilises concepts of the stream and data-parallel paradigms to generate synthesisable co-processors targeting a commercial platform SoC Field-programmable gate array (FPGA). Open computing language (OpenCL) was used which is an industry supported data-parallel programming standard for writing programmes that execute on heterogeneous platforms and accelerators comprising Central processing unit (CPU)s, Graphics processing unit (GPU)s and other forms of accelerators.
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Record Number: 15641 / Last updated on: 2013-06-12