Development of Josephson junction arrays
The report describes the work carried out at PTB for the development of 1 V and 10 V standards based on monolithic arrays of multiple Josephson junctions, fabricated in the Nb/Al(2)O(3)/Nb technology. The process employed for the fabrication of the chip is presented in detail, then the merits of these arrays as room temperature references for the calibration of secondary voltage standards are discussed. The results of long term (1 h) stability tests are given, which prove that the arrays do provide a stable reference voltage, limited in precision only by the noise of the associated instrumentation.
Bibliographic Reference: EUR 13579 EN (1991) 127 pp., FS, ECU 11.25
ISBN: ISBN 92-826-2022-0
Record Number: 199111016 / Last updated on: 1994-12-02
Original language: en
Available languages: en