Edge loading of plasma facing components in fusion devicesFunded under: FP2-FUSION 10C
The new poloidal and the inner wall guard limiter tiles of JET have been shaped to maximise power handling capability. The existing design of the divertor tiles of JET has been modified to reduce edge exposure. All of these components consist of discrete tiles with finite gaps. Under the assumption that the particle power flow is along field lines, the leading edges of the tiles are exposed due to field line penetration between gaps. The peak loading of these tiles is to be at the edges. The report presents a generalised solution to the edge problem which indicates the steps required to shape the tiles for maximum power handling capability.
Bibliographic Reference: Report: JET-R(93)01 EN (1993) 19 pp.
Availability: Available from the Publications Officer, JET Joint Undertaking, Abingdon, Oxon. OX14 3EA (GB)
Record Number: 199310676 / Last updated on: 1994-11-29
Original language: en
Available languages: en