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H2020

AXIOM Report Summary

Project ID: 645496
Funded under: H2020-EU.2.1.1.1.

Periodic Reporting for period 1 - AXIOM (Agile, eXtensible, fast I/O Module for the cyber-physical era)

Reporting period: 2015-02-01 to 2016-01-31

Summary of the context and overall objectives of the project

1.1 Summary of the context and overall objectives of the project
We are entering the Cyber-Physical age, in which both objects and people will become nodes of the same digital network for exchanging information. We imagine that the general expectation is that “things” or systems will become somewhat “smart,” allowing rapid and close interactions not only system-system, but also human-system and system-human. Scientifically speaking, we expect that such Cyber-Physical Sys-tems (CPSs) will react in real-time, have enough computational power for the assigned tasks, consume the least possible energy for such tasks (energy efficiency), scale up through modularity, allow for easy programmability across performance scaling and exploit at best existing standards at minimal costs. These expectations impose scientific and technological challenges that need to be properly addressed.
The AXIOM project (Agile, eXtensible, fast I/O Module) aims to research new software/hardware architectures for CPSs to meet the above expectations. The technical approach aims to solve fundamental problems in order to enable easy programmability of multi-core, multi-board systems through the open-source OmpSs programming model, leveraging Distributed Shared Memory (DSM)-inspired concepts across the modules. OmpSs will allow accelerating functions through reconfigurable hardware (Agility). To the best of our knowledge, this is the first time that DSM will be demonstrated to be effective on an embedded modular system (eXtensibility). Modular scalability will be possible thanks to a fast interconnect that will enrich the module. To this aim, an innovative modular ARM-based board with enhanced capabilities for interfacing with the physical world will be designed and demonstrated in key scenarios such as Smart Video Surveillance and Smart Living/Home (Domotic).

Work performed from the beginning of the project to the end of the period covered by the report and main results achieved so far

1.2 Worked performed from the beginning of the project to the end of the period covered by the report and main results achieved so far
The work has been subdivided into seven work packages, including project management (WP1) and dissemination and exploitation (WP2), which are necessary for achieving the ambitious goals of the project. As for the technical work packages, in the first year, the focus was on defining scenarios for the two do-mains considered in this project, namely Smart Home Living (SHL) and Smart Video Surveillance (SVS). Scenarios definition was the output of the following process: i) A review of trending applications/services in the domain of Smart Video Surveillance and Smart Home Living; ii) A collection of scenarios envisioned by the partners in the consortium; iii) A survey of current reconfigurable hardware (FPGA) products and projects. The activities in WP4 focused on extending the OmpSs programming model so that easy programmability could be achieved in embedded systems that include FPGAs and that are made of several boards, as in a small cluster. To do this, the necessary parts of the software stack were developed to properly manage the distribution of code and data at low level through, e.g., appropriate DMA engines and soft-IPs. The mechanisms for implementing data transfers on the FPGA platform have also been evaluated in order to perform the proper selection during the implementation phase. In WP5, the operating system’s re-lated parts were designed and the necessary software interfaces (API) were drafted with the contributions of the interested partners. In WP6, the architecture of an initial prototype of the AXIOM board was de-fined. The first prototypes will be available to the partners during the second quarter of 2016. This initial prototype is based on a 32-bit architecture, which initially seemed to be an interesting entry point for AXI-OM-based systems, although now a more powerful 64-bit architecture is under consideration. A first prototype of the AXIOM-link interconnect has already been demonstrated. In WP7, the initial evaluation plat-form was defined. This evaluation platform is based on both a full-system simulator and on the FPGA development boards. In order to flexibly explore the possible design points, Design Space Exploration tools were developed and made available to the partners. The XSMLL API (a DSM-inspired interface) for managing threads was successfully demonstrated on the simulator. In terms of preliminary results of tests on thread distribution across boards, experiments with an appropriate consistency memory model to overcome classical DSM limitations were presented to the public.

Progress beyond the state of the art and expected potential impact (including the socio-economic impact and the wider societal implications of the project so far)

1.3 Progress beyond state-of-the-art and expected potential impact (including socio-economic impact and wider societal implications of the project so far)
In our view, and according to known roadmaps for future systems, the key problems for a wider deployment of scalable embedded systems are: i) easy programmability; and ii) inexpensive ways to build systems based on simpler components.
The AXIOM project has defined a simple but powerful architecture that can possibly be deployed in Cyber-Physical Systems (CPS), since it will include not only classical embedded system components and the possibility to connect to the Internet, but also the possibility of easily building CPS from two or more boards, without changing development tools (i.e., the programming model). We will release the specifications of this new system both as open-hardware and open-source software. Moreover, the reconfigurable logic is part of the system thus allowing a larger degree of flexibility to interface any type of peripherals.
To the best of our knowledge, no similar effort exists in the Embedded System and CPS communities, so we hope it will be welcomed as were similar boards like the RaspberryPi and the UDOO (this latter built by one of our partners and currently one of the top ten boards used by maker communities).

Related information

Record Number: 186489 / Last updated on: 2016-07-13
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