Community Research and Development Information Service - CORDIS

Periodic Report Summary 1 - ASIVA14 (Analog SImulation and Variability Analysis for 14nm designs)

Electronics industry requirements make electronic design automation (EDA) a very challenging engineering and research area. Commercial and industry simulators have made tremendous enhancements in speed, capacity and functionalities over the past years, but there are still technical gaps rendering most current EDA methods and the tools that support them inadequate to the task of designing for the “real world”. The S&T objective of the ASIVA14 project is to rigorously deal with current shortcomings in the simulation of analog/mixed-signal circuits, and address a number of important technical gaps.

Another motivation for this training network is the need for a network of highly educated European scientists in the field of mathematics for the EDA industry and computational science, so as to exchange and discuss current insights and ideas, and to lay groundwork for future collaborations. The challenge lies in the necessity of combining transferable techniques and skills such as mathematical analysis, sophisticated numerical methods and stochastic simulation methods with deep qualitative and quantitative understanding of mathematical models arising from problems in the electronics and EDA industry. The main training objective is to prepare, at the highest possible level, young researchers with a broad scope of scientific knowledge and to teach transferable skills. The two partners in the project combine decades of knowledge on EDA problems, and as such are an ideal basis for the hosting of the young ESRs to be trained.

The three ESRs appointed in the project concentrate on the following technical gaps:

1. Develop, implement and test efficient and powerful numerical methods for nearly periodic analogue circuit simulation that drastically reduce computation times
2. Develop, implement and test fast and scalable numerical methods for transient circuit simulation enabling full chip verification
3. Develop, implement and test new numerical methods allowing fast parametric simulations and reducing the required number of Monte Carlo runs for the variability analysis of Analog IP blocks.

ESR1 and ESR2 started their research and training with a thorough study of model order reduction (MOR) methods for nonlinear problems, most notably the popular and very effective DEIM method. By combining it with POD (proper orthogonal decomposition) they came up with the methods EDEIM (extended DEIM), and later GDEIM (generalized DEIM) to address nonlinear circuits. After extensive testing and modifying the methods accordingly, a write up is now available that will be published in a suitable journal.

ESR1 the set off to concentrate on nearly periodic circuits. He studied the methodology developed for MOR of voltage controlled oscillators (VCO), and then developed a framework to decouple the VCO from the rest of the circuitry and replace it by a phase noise model. Currently this methodology is being tested. ESR2 left the project after having finished the work on GDEIM, and was replaced by a new early stage researcher just before the end of the first period.

ESR3 entered the project at the start of the second year, and first performed a literature study as well as a training into statistical aspects of electronic circuit simulation. He also studied methods for uncertainty quantification, but concluded that these may be abandoned for the time being because of the large dimensions of the problems to be addressed. In the final part of the first period, he developed an emulator technique to speed up the rather long simulation times for statistical and Monte Carlo simulations. In this technique, the original simulator is replaced by an emulator that is based upon a data set of existing and known simulations. The method is currently being tested, as well as assessed for its application to high dimensional problems.

In this first period, some very interesting observations have been made, and the development of GDEIM led to a very nice methodology that can be used also for other application areas. The real research work into addressing the aforementioned 3 challenges has started essentially at the end of the reporting period, and will be accelerated in the second period of the project. We are confident that the work on nearly period circuits will lead to new methods that speed up the simulations considerably. For challenge 2, a number of new research directions has been identified, which will also be explored. The emulator technique developed by ESR3 is useful for problems with up to 15 dimensions, but it is clear that work will need to be done to increase this to higher dimensional situations.

All three ESRs entered the PROOF program for PhD students at TU Eindhoven, where additional skills are being trained as well as an introduction to scientific integrity is being given. At Mentor Graphics, all three ESRs have received training into EDA software tools, and learned how to use the software developed inside the company. They have attended several conferences, both at the national and international level, and did poster presentations (including poster blitz) at most of these events.

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