Community Research and Development Information Service - CORDIS

Final Report Summary - HYPERCONNECT (Functional joining of dissimilar materials using directed self-assembly of nanoparticles by capillary-bridging)

Executive Summary:
The worldwide economy and society were and are benefiting heavily from the miniaturization of electronic devices enabling a myriad of novel smart products with additional functionality in the consumer and high-performance sector at ever decreasing cost. Miniaturization (Moore's law) has been the main driver for this trend in the last decades. One possible approach to support further device miniaturization is the so called 3D chip stacking. Thereby, individual semiconductor dies are stacked on top of each other and are electrically connected. A major challenge today, and therefore a limitation, is the reliable joining of dissimilar materials supporting efficient heat dissipation and sufficiently small electrical interconnect pitches within and to the chip stack. HyperConnect addresses all these challenges by a radically new method to join dissimilar materials and specifically form superior thermal and electrical joints. A novel sequential joint formation methodology decouples dependencies between material properties up till now considered as limiting factors in electronic packaging. It also enables the neck formation of functional nanoparticles by directed self-assembly using capillary-bridging between point contacts of filler particles in a matrix or between interconnects and pads. The combination of both methods yields the unprecedented joint properties, which are:
• Percolating thermal underfill with 7-fold improved thermal conductivity compared to mechanical underfills
• All-copper interconnects formed at 200°C on standard manufacturing equipment
• Improved electrical contacts of metal coated polymer spheres applied in conductive adhesives

Project Context and Objectives:
The objective is to demonstrate superior electrical, thermal and thermomechanical performance and to combine design and technology with the support of simulation and testing. The central new idea comprises a sequential joint forming process exploiting capillary action and chemical surface functionalization to achieve self-assembly of nanoparticles.
• Develop radically new joining technology for electronic applications based on materials design
• Verify its superior electrical, thermal and thermo-mechanical performance on demonstrator level
• Target: 10x increase in thermal conductivity; 5x improvement of reliability at very reduced pitches
• Generate fundamental understanding of neck formation process as a multi-material and multi-scale phenomenon
• Prove manufacturability and identify risks of novel joining technology on four demonstrators

Project Results:
The main achievements of the HyperConnect project can be clustered in three categories. They are:

Percolating thermal underfill (PTU):
• Epoxy with low viscosity and long gelation time
• 7-fold improved thermal conductivity with PTU
• Server form factor 3D chip stacks filled with PTU
• PTU formulation without failure after 500 thermal cycles

Neck-based electrical interconnects (NEI):
• Metal coated polymer spheres with a superior Ag quality enabling thermomechanical reliability improvements when applied in a conductive adhesive drastically outperforming alternative interconnect solutions
• Cu-paste formulation to be sintered at 200 °C for 15 minutes
• Robust process to achieve all-Cu interconnects by dipping and screen printing
• Characterization and simulations of porous Cu-samples enabling failure predictions

• Efficient method to derive the master curve and Prony series by sub-domain modelling at minimal experimental cost

Potential Impact:
The following HyperConnect outcomes will be exploited by the industry partners (details about the exploitation plan are confidential):
• Percolating Thermal Underfill (PTU)
• Low viscosity matrix material
• Metal coated polymer sphere based interconnects
• All-Cu interconnects
• Advance mix mode bending tool

The impact on system performance by applying the PTU could be evaluated and concluded to be substantial. The development of the PTU thereby support further scaling of 3D chip stacks with respect to larger number of stacked dies and/or higher dissipated heat flux levels. For high-performance chip stacks with heat fluxes >20 W/cm2, four-die stacks will now be feasible and it will be possible to increase the clock frequency by 200 MHz for two-die stacks. The benefits of the PTU are even larger for memory stacks with more than four dies in a stack since several more interfaces are present. Considering a 16 die stack, a 200% heat flux improvement can be expected if all interfaces filled with capillary thermal underfill are rather filled with the PTU solution. For the NEI, electromigration investigations need to be completed to derive a quantitative system performance impact by a potential improved current density.

List of Websites:

Related information

Documents and Publications


Catherine Trachsel, (European Projects Advisor)
Tel.: +41 44 724 8289
Fax: +41 44 724 8578
Record Number: 188137 / Last updated on: 2016-08-11