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H2020

SEPHY Report Summary

Project ID: 640243
Funded under: H2020-EU.2.1.6.1.

Periodic Reporting for period 1 - SEPHY (SPACE ETHERNET PHYSICAL LAYER TRANSCEIVER)

Reporting period: 2015-05-01 to 2016-04-30

Summary of the context and overall objectives of the project

The growing complexity of space systems is creating the need for high speed networking technologies to interconnect the different elements of a spacecraft. This interest has spurred initiatives by both ESA and NASA to define the next generation networking technologies for Space. In both cases, Ethernet has been the preferred choice due to its wide adoption in terrestrial applications and because it is fully specified in standards to ensure interoperability. The requirements for integrated circuits that have to operate in space are very different from those that are used in terrestrial applications. In particular, the radiation is much more intense and causes several types of effects on the devices that compromise their reliability. Therefore, special “rad-hard” design and manufacturing techniques are needed for devices that will operate in space. This means that to implement Ethernet in space systems, rad-hard Ethernet components have to be designed. The goal of this proposal is to design and manufacture rad-hard Ethernet PHYs (Physical layer transceivers). In particular a 10/100Mbps PHY is targeted as the first short term objective. This device will enable the use of Ethernet in space systems and also provide the starting point for the long term objective of implementing a Gigabit Ethernet PHY for space. To that end, the proposal includes a feasibility study and also contributions to the 1000BASE-T-1 Ethernet standard.To implement the Ethernet PHYs, the consortium has significant analogue (Arquimea) and digital (IHP) design capabilities. In addition, it has also experience on the upper layers of Ethernet and its use in Space systems (TTTech) and on the design and implementation of Ethernet PHYs and Ethernet standards (Universidad de Nebrija). Finally, the electronic technology and manufacturing capabilities are also covered (ATMEL) as are the space system perspective and testing (Thales Alenia Space Spain).

The main objective of this project is the development of a radiation hardened 10/100 Ethernet physical layer transceiver for the space market that could enable Ethernet based technologies to become an international space standard in future applications. An additional objective is to study the feasibility of a Gigabit Ethernet physical layer transceiver for space as the natural evolution of the 10/100 one and also to make sure the future IEEE 802.3 standards over a single twisted pair take into consideration the space sector requirements.

Work performed from the beginning of the project to the end of the period covered by the report and main results achieved so far

During the first year of the project most of the goals presented for this timeframe have been achieved however some activities have incurred in delays so the overall project planning has suffered a small deviation. The project has followed the functional organization reflected in Figure 1, with WP1, WP7 and WP8 taking place in parallel and WP2 to WP 6 in series one after the other.

As the project kicked off, WP1 and WP8 started to run immediately taking care of the management and dissemination/exploitation tasks. Once the operating procedures of the project where closed, WP7 was launched to always keep an eye on the future roadmap and on the standardization activities related to SEPHY that were taking place. At that same time, the activity that took care of the gathering of system level requirements for the PHY development started (WP2). This work package was successfully closed in the Requirements Review meeting providing the project with a first analysis on the feasibility of SEPHY and the set of system level requirements needed to proceed to the next step of the development. WP3 started right away to provide a first approach to the overall PHY architecture as well as to draw the main guidelines to be followed on the future verification of the ASIC. The Architectural Design Review formally closed WP3 with a reference architecture and a verification procedure available.

Once WP2 and WP3 were closed, the actual PHY design started. As detailed in Annex 1 of the Grant Agreement, work packages 4, 5 and 6 are conceived in phases as presented in Figure 2. In this first annual review only the design activities of the first phase were (and finally have) taken place. The goal of the phase 1 chip was to be able to prototype the most critical blocks of the Ethernet Transceiver, especially for 10BASET, i.e: the ADC, the DAC, the line drivers, the MII interface, the clock scheme and the 100BASE-TX adaptive equalizer. Although these blocks were tentative at proposal time, most of them were indeed conceived as critical and were finally implemented in the phase 1 run. Nevertheless, due to some delays on the digital side activities most of the digital logic was finally left out of the first run and will be validated in an external FPGA during test.

By the time the first annual review took place (30/04/2016) the available Multi Project Wafer fabrication windows had a slight modification w.r.t the ones originally conceived in the proposal so the phase 1 tape-out was scheduled to happen on 08/07/2016.

The next paragraphs include a more detailed review of each work package indicating their status, goals, achievements and deviations so that this overall project status can be understood in detail.

WP1: Project management
The consortium organization has been completed and continuous management between all partners has taken place. A set of documents, meetings and milestones have been completed in this period with small schedule deviations. The Requirements review meeting took place in July, as originally planned. Likewise, the Architectural Design Review took place in October. The main schedule deviation which affects indirectly the activities that took place on the first year was the tape-out date shift of the first phase. The first tape-out was originally planned to be in May 2016 however the MPW windows available showed that the closest one available was the 8th of July 2016. Although this change is related to dates on the second year of the project, the design activities were slightly affected by it as will be discussed later.

Deviations from planned future activities mainly affected by the need to align the project schedule with MPW windows will be discusses in Appendix I: Recovery plan for future activities.

The following documents were issued to consolidate the basis of the consortium:
• D1.1 – Consortium operating procedures
• D1.2 – Key project indicators

The following project milestones took place within this period:
• M1 – Kick Off Meeting (02/06/2015) at REA.
• M2 – Requirements Review (29/07/2015) Teleconference.
• M3 – Architectural Design Review (20/10/2015) at IHP headquarters.
• M4 – PDR and 1st Annual Review (30/04/2016) at REA. This meeting was originally planned to take place in Madrid however due to programmatic restrictions it was finally held in Brussels. It was agreed to move the final review meeting (project closure) to Madrid so that overall travel budgets do not change.

Additionally during this reporting period, CERN has showed interest on the SEPHY device and conversations have started to identify common goals and the potential inclusion of CERN in the project. These conversations are expected to continue in the coming months.

WP2: Requirements definition
The consortium lead by TTT and TASE, as final users of the PHY, compiled a list of the main system level requirements of SEPHY that could be used as starting point for the chip implementation. Additionally, a preliminary assessment on the feasibility of the device was made identifying the most complex and risky elements. Two documents were completed in this WP:

• D2.1 – Requirements Specification Document.
• D2.2 – Feasibility and Risk Assessment Document

The outputs from this work package were used as inputs on the next one: WP3 Ssytem Design and Verification

WP3: System Design and Verification.
The main goal of this work package was to define the chip architecture down to the level of basic blocks and their intended functions, their interfaces and interactions. Especial attention was made to the blocks that were targeted on phase 1 so that the detailed design on those blocks could easily start once the architecture was closed. Additionally in this work package the overall verification procedure was outlined and will be used as reference for the future verification and tests phases. Three documents were completed in this WP:

• D3.1 – Architectural Design Document
• D3.2 – Verification Procedure at block level
• D3.3 – Verification Procedure at transceiver level

The architectural design document is planned to be a live reference that would be updated in phase 2 when the detailed architecture of the 100BaseTX blocks is revisited.

WP4: PHY design and verification.
In this work package, the design and the verification of the phase 1 chip has taken place. The main objective of this first prototype was to implement the most critical blocks of the Ethernet transceiver, especially those related to the 10BASET operation. In Annex I of the Grant Agreement it was foreseen to tape-out in this phase at least the ADC, the DAC, the 10BASE-T line driver, the 100BASET-TX line driver, the MII interface, the clock scheme and the 100BASE-TX adaptive equalizer. At the end, all those blocks have been included with the exception of the 100 BASE-TX line driver, the adaptive equalizer and the MII interface. The 100BASE-TX driver was finally excluded to dedicate more effort on the 10BASET part where two line drivers where included one with cold spare capability and another one without it. The rest of the blocks that have been excluded are digital ones. The digital part of the design has suffered a significant delay due to the following reasons:

• It took longer than expected to agree on the design flow to be followed on the digital side and what views of the Design Kit were needed by IHP.
• Management issues w.r.t the signature/approval of the Addendum to the DELA (several iterations required). This document reflects all legal aspects related to the Design Kit access.
• Design not fully available at the required time due to a lower allocation of resources than expected.

Despite this fact, the phase 1 chip was thought in such a way that all the digital logic that was not finally included on it could be later programmed on an external FPGA. In this way the digital functionality could be tested along with the phase 1 chip aiming most of the full SEPHY functionality and adding an extra layer of flexibility since the digital logic on the FPGA could be reprogrammed if needed.

This work package has also been influenced by the fact that the Multi Project Wafer window available for fabrication was fixed to be on July instead of the originally planned moth of May. This forced the modification of the overall schedule to align the dates to the available time window. Thus, this work package finally lasted approximately one month and a half more and this extra time was used to improve the analogue and mixed signal block level simulations.

Six documents were completed in this WP:

• D4.1 – Design Guidelines
• D4.5 – Preliminary Datasheet (This document was originally foreseen as SEPHY Digital controller Preliminary Datasheet however it was agreed to rename it as D4.5 and provide not only the information related to the digital side but also to the whole ASIC)
• D4.6 – Digital Logic Verification Plan and Report 1
• D4.10 - ASIC Requirements Specification (This document was originally foreseen as Prototype Detailed Analogue Design Document but its contests where redundant with D4.18 Detailed PHY Design Document 1. Instead it was agreed to provide as D4.10 the actual ASIC requirements specification)
• D4.11 – Prototype Analogue Design Verification Plan and Report 1

WP7: Roadmap and Standardization
The main objective of this WP is to provide a long term roadmap and vision for Ethernet transceivers in space systems. During this period, a first analysis on the requirements for a 1Gb/s space PHY was made and different options for a future improvement of SEPHY were discussed amongst the partners. One document was completed in this WP:

• D7.1 – Report on Requirements for space grade 1Gbps.

WP8: Dissemination Exploitation and Communication
This Work Package deals with all the dissemination and communication activities on one hand and with the Exploitation related ones on the other.

Before starting the dissemination activities per se, in the frame of this work package the project logo and its factsheet were designed. Additionally a flyer was printed so that it could be distributed in congresses and fairs. Finally a Webpage, a LinkedIn and Twitter accounts were set up to promote the project and improve its visibility.

A dissemination plan was compiled and dissemination activities started. A few congresses and workshops were attended were the project was presented and promoted. As part of these activities a contact with CERN was made and, as described in the WP1 section, further communication started.

With regards to the actual exploitation of the SEPHY device and as stated on the Consortium Agreement clause 8.5, the commercial exploitation of the PHY has been coordinated by ARQUIMEA (as owner if the chip) and involved those parties that expressed interest to the commercialization: TTTECH and ATMEL. It was agreed that these parties will be the ones directly on the commercialization of the device.

Seven documents were completed in this WP:
• D8.1 – Project factsheet and logo
• D8.2 - Website and Social Network Profiles
• D8.3 - Dissemination Plan 1
• D8.4 - Dissemination Plan 2
• D8.7 - Dissemination Report 1
• D8.12 - Cost Analysis 1
• D8.15 - Exploitation plan and market analysis

Progress beyond the state of the art and expected potential impact (including the socio-economic impact and the wider societal implications of the project so far)

The ambition of the SEPHY project is to put Europe at the forefront of the adoption of Ethernet PHYs in space systems. This goal is ambitious as 1) the Ethernet commercial and industrial IC market is dominated by non-European companies (Intel, Broadcom, Marvell, LSI, etc. and 2) Ethernet PHYs are complex mixed signal devices and there are no Ethernet PHYs qualified for space. Since the PHYs are a key component in Ethernet, the success of SEPHY would not only ensure non dependence but possibly also leadership position over other countries. Therefore the goals are ambitious both technically and in terms of the long term strategic impact of the project.

The SEPHY project also has the ambition to reuse the developed PHYs for other mission critical applications. Those include automotive, avionics and industrial systems in which Ethernet is already or is likely to be the dominant networking technology. This extends the ambition of the proposal beyond space systems. Extending the use of the SEPHYs for terrestrial applications could help in positioning Europe as a player in the Ethernet IC market (which is a large market with more than one hundred million devices sold every year).

The project also includes (in WP7) forward looking activities to enable the future development of a Gigabit Ethernet PHY for space. This work is highly innovative and involves the use of advanced signal processing, communications and electronics (analogue and digital). Also within this WP contributions to the Reduced Twisted Pair Gigabit Ethernet (1000BASE-T1, IEEE 802.3bp) standard will be made to make it suitable for space applications. This is a unique opportunity as this new standard will require only one twisted pair compared to four of the current standard (1000BASE-T). This will reduce the weight of the cabling which is an important factor for space systems.

Additionally, a study and implementation of advanced mitigation techniques for single events effects will be done in WP4.3. In particular, the research of UAN on fault tolerant signal processing implementations will be used to optimize the protection of the PHYs. This can result in lower costs compared to existing mitigation techniques. Additionally IHP will also investigate novel mitigation techniques at architectural level to improve the overall digital implementation reliability. Finally, UAN will also investigate on power efficiency in WP4.4 to provide a beyond state of the art PHY also in terms of power consumption.

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