Community Research and Development Information Service - CORDIS

Final Report Summary - INFO-STORE (Novel Data Storage by Advancing Information Sciences)

In the InfoStore project under the Marie Curie CIG action, we made important progress on improving the performance of emerging data-storage applications through innovations in the information sciences. Touching on many applications from non-volatile storage devices to network switches, we have developed a multitude of mathematical frameworks to make these technologies better.

To maximize the impact of the project and the value it offers to real-world information-storage, we pursued the following general flow of research. A project starts from discussions with industry/academia experts in a certain data-storage domain. Then we identify an information-related problem that can be solved by tools within the information sciences. The main research activity is to work a theoretical framework that will be able to solve the identified problem with high efficiency and significant flexibility, matching the varying circumstances of real applications.

We detail the project's contributions by first listing in List 1 the data-storage applications and specific problems we addressed. Each item in List 1 has a matching item in the subsequent List 2 detailing the corresponding research achievements.

List 1: applications and problems
1) Multi-level non-volatile memories and their tradeoff between storage density and read/write speed.
2) High-throughput memory systems for network switches and routers.
3) High-density memristor storage and its associated reliability challenges, and computing promises.
4) Reliability of multi-level non-volatile storage devices.

List 2: research achievements
1) We have contributed a series of papers toward improved tradeoffs between density and speed in multi-level memories. We studied efficient algorithms to read memory cells in parallel. Then we developed coding frameworks by which we can maximize write and read speeds for any specified storage density (or vice versa: maximize storage density per specified read/write performance). In another direction we developed a coding scheme using efficient iterative-decoding algorithms, which deals with partial readouts, for example when the read circuitry outputs only partial information on the stored memory level. Under the same objective of improving multi-level non-volatile memories, we also developed optimal multi-write codes that maximize the number of writes into the memory before a costly erase operation is invoked.
We developed a performance coding scheme that allows the storage device to choose between more storage or more access speed in a flexible manner, while using only a single media type. We envision a storage device with two (or more) write paths, where in each one a different encoder maps information to physical media states, optimizing access speed in one and storage density in the other. By implementing two such encoders the device mapping layer can choose on a per-command basis whether the particular read or write needs more speed or more density. Our coding scheme considers natural and realistic read/write models for non-volatile memories, and provides the mathematical formulation to optimize read/write performance and storage density in these models.
2) We have addressed the problem of memory contention in network switches and routers by coding the packets upon their arrival to the switch (and decoding back to pure uncoded packets prior to their departure). Our results enable to improve the switching rates in these central networking devices. Memory contention in these systems occurs at the packet read path, when multiple packets are requested by the controller from the same memory bank at the same time. We develop two approaches to solve this: A) Guaranteed readout: where a special type of code -- called "switch code" -- guarantees a full-rate readout for any requested set of packets, and B) Flexible readout: where standard MDS or cyclic codes are used cleverly to reduce contention and increase the read throughput. In approach A, the contributions are constructing codes that guarantee full parallel reconstruction of all input packets. In approach B, the contributions are developing the policies used for placement of coded packets, the algorithms to read maximal sets of packets, and the analysis of the resulting switching throughput.
3) Resistive memory (also known as memristor) is the most promising storage technology beyond the commercial technologies of today. Toward having resistive storage in reality, we developed an information-theoretic framework for the reliability of the read and write processes in the presence of heavy inter-cell interference. This interference is called "sneak paths", and it is the result of the extremely dense crossbar structure of the memory-cell layout. In addition to reliability, we also developed a scheme to use resistive arrays for in-memory computation in machine-learning applications. Performing computations in memory saves the time and energy required to dispatch high data volumes to and from the central processor. In this research we consider a memory device that stores a large number of binary vectors. Each 0/1 vector element is mapped to a primitive resistive element that is in high/low resistance state, respectively. The problem we solve is how to use the resistive physical medium to compute similarity between pairs of vectors within the memory array. In particular, we show how coding the data vectors can significantly improve performance. In another memristor-related work we showed how computing and storage can be combined using regular arrays of memristor devices combining storage and logic.
4) Multi-level memory cells are used in non-volatile memories (NVMs) to increase the storage density, and scale the storage capacity of mass-storage devices. Using multi-level cells, however, imposes higher error rates and deterioration of data reliability. Ensuring the reliability of high density NVMs is currently the most fundamental problem of data-storage devices. Toward that end, our research developed a novel constraint-based coding scheme that combats the most dominant error type of multi-level NVMs – asymmetric errors of magnitude 1. For moderate to large numbers of such errors, the scheme is shown to deliver better correction capability compared to known alternatives, while admitting low-complexity of decoding.

These contributions of new frameworks are attracting great interest from both academia and industry. We have published these results in the top conferences and journals of the information theory field, and in addition in leading venues for storage devices and systems. We emphasize the practicality of the schemes in the latter, and their depth in the former. In addition to top-tier publications, these contributions are now being examined for implementation by leading technology corporations in the respective engineering domains. Both internationally and locally in Israel, there are several companies that are busy addressing these major challenges reported here. Our new fresh ideas and the deep schemes accompanying them may be found useful toward solving these challenges as the next-generation products are being contemplated.
More details on the project can be found on the PI's website:
http://ycassuto.eew.technion.ac.il/

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