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PowerBase Report Summary

Project ID: 662133
Funded under: H2020-EU.

Periodic Reporting for period 1 - PowerBase (Enhanced substrates and GaN pilot lines enabling compact power applications)

Reporting period: 2015-05-01 to 2016-04-30

Summary of the context and overall objectives of the project

Power Semiconductors are key drivers for the innovation capability of European industries, large and small, generating economic growth and supporting meaningful jobs for citizens. They offer solutions to some of the difficult societal challenges addressing European policies for 2020 and beyond. For both reasons, it is vital that investments are made to assure European collaboration and the access to the technologies, know-how and capacities, which guarantee growth potential and strategic independence in the face of increased globalization.
The European semiconductor ecosystem employs approximately 250,000 people directly and is at the core of innovation and competitiveness in all major sectors of the economy. PowerBase will directly impact the semiconductor production in Europe, aligned with the electronics strategy of the European Commission.
The project PowerBase aims to setup and enhance power semiconductor manufacturing pilot lines in the area of wafer production and chip embedding in packages with special attention on compact power applications. Demonstrators and full-scale testing are essential building blocks of the PowerBase project proposal meant to stepping up Europe's innovation capability by the development of technologies in the area of energy efficient systems. This will provide Europe with reinforced means to significantly raise its competitive edge across the economy and to address its key societal challenges.
Electronic components and systems (ECS) is a domain with a worldwide fast growing market. European companies have dominant global positions in key application areas for Europe, such as efficient use of limited energy resources, as well as in equipment and materials for worldwide semiconductor manufacturing. The underlying technology domains are also extremely R&D intensive, with semiconductor industry investments reaching 20% of total revenues.
The key objective of ECSEL is: “Ensure the availability of ECS for key markets and for addressing societal challenges, aiming at keeping Europe at the forefront of the technology development, bridging the gap between research and exploitation, strengthening innovation capabilities and creating economic and employment growth in the European Union. The project PowerBase aims to contribute to the industrial ambition of value creation in Europe and fully supports this vision by addressing key topics of both “Strategic Thrusts”: “Key applications” and “essential Technologies (capabilities)”. By positioning PowerBase as an innovation action a clear focus on the exploitation of the expected result is a primary goal.
To expand the limits in current power semiconductor technologies the following main goals will be targeted by the PowerBase project:
• Development of advanced carrier substrate technologies for improved GaN material quality and reliability for next generation GaN based power devices
• Setup of a qualified wide band gap GaN technology pilot line based on 200mm wafers for high performance normally off GaN power transistors including GaN-on-Silicon epitaxy with advanced process control, high manufacturing stability and yield
• Expanding the limits of today’s 300mm silicon based substrate materials for power semiconductors in two directions: First on the low ohmic substrates and second at high ohmic substrates by introduction of advanced doping materials and power device processes.
• Improving manufacturability in a high volume / high automated fab as being key for cost competitiveness: work on advanced automation
• Enhance system compatibility by introducing advanced packaging solutions out of a dedicated chip embedding pilot line
• Demonstrate results and reliability in leading compact power application domains

The impact of PowerBase will be huge on both paths, the silicon path and the wide band gap path enabling major advancements in the area of MtM and SiP.
PowerBase is a project proposal with a vertical supply chain involved. This spans expertise and partners from raw material research, process innovation, pilot line, assembly innovation and pilot line up to various application domains representing enhanced smart systems. The supporting partners consist of market leaders in their domain, having excellent technological background, which are fully committed to achieve the very challenging project goals, complementing each other in a well-balanced and structured way avoiding overlaps and missing expertise.
Main application fields have been selected as demonstrators. Amongst many others these are: energy conversion in main’s application where size matters like portable devices or lighting applications and photovoltaic energy generation as one element in the future energy supply chain, which gets with technological progress more and more in focus for decentralized local energy supply. The envisioned innovative power components address highest efficiency and reliability in energy generation, transformation and usage. Highest efficiency and reliability at a reasonable price per power unit are the key characteristics for a successful participation in a global and international market.
The project PowerBase also aims to have significant impact on smart regions. High tech jobs in the area of semiconductor technologies and micro/nano electronics in general are expressed core competences of the regions Carinthia and Styria (both Austria), Saxony and Bavaria (both Germany) and many other countries involved.

Work performed from the beginning of the project to the end of the period covered by the report and main results achieved so far

"The project started on 1st of May 2016. During the first year all Deliverables and Milestones as well as the reports (M06 and M12) have been delivered in time. No major risks did materialize. The cooperation between the partners was very intense and highly productive.

***Project Management:
The full consortium did sign the Consortium Agreement before the Grant Agreement was signed. The Kick-Off meeting took place in May 2016 at IFAT in Villach, Austria and the project was established with all Management bodies necessary. A M06 Meeting (University of Graz, Austria) and a M12 Meeting (imec, Leuven, Belgium) took place with an intense Face-to-Face meeting of all Workpackages. The contact an cooperation between the Coordinator and the Project Officer is intense and very positive.

***Objective 1: Innovation on advanced carrier wafer technologies for GaN devices (Workpackage 1)
- Description:
Beside the rather expensive pure GaN substrates, the GaN-on-Si power technology is presently in a nascent state characterized by a range of technology and infrastructure constraints, which confine the commercialization space. To cope with these constraints, enhancements for GaN on Si including other advanced carrier materials will be investigated.
- Work performed and main results achieved towards Objective 1:
For the advanced carrier wafer technologies for GaN, there is an industrial track, for which EpiGaN has been optimizing their GaN-on-Si process to further push the limits of GaN technology. They have achieve a significant reduction in leakage current and buffer induced current collapse in the past period.
The second track is the investigation of advanced carrier wafers and processes which can improve on the performance of GaN-on-Si. There are three classes of novel carriers being investigate, namely engineered Si, Si with interlayers and alternative CTE matched carriers. In the past period it was demonstrated that engineering the Si by doping can either create more rigid wafers for GaN growth with reduced slip lines or achieve a higher breakdown (100V higher) with a similar thickness of GaN buffer. The interlayers under investigation have been Er2O3 and SiC. Growth and optimization of buffers has been performed on both interlayer types. On the wafers with Er2O3 it was not possible to grow a GaN buffer due to a too large lattice mismatch. On the SiC on the other hand the growth was possible, but performance is still limited due to defects originating from the SiC interlayer itself. For the CTE matched substrates; a process has been developed for growth on poly-AlN wafers. These wafers were successfully introduced in the pilot line and imec has been able to grown a GaN buffer on these layers, showing an reduction in leakage with an order of magnitude compared to a similar GaN buffer grown on a thicker Si(111) carrier. An alternative CTE matched carrier is Mo, these wafers are being developed in powerbase by Plansee. The first 200mm Mo substrates have been fabricated with a good surface morphology, wafer bow and compatible wafer bevel. The wafers possess a risk of contamination due to bulk contaminants and work is still on-going to evaluate pilot line compatibility.
The third track is looking even further ahead to fabricating bulk GaN wafers and increasing their wafer diameter; FCM has been developing technology for growing free standing (bulk) GaN wafers on 3 inch. Improvements have been achieved in wafer quality by switching to a HVPE tool with an alternative gas flow geometry. While for uniformly doping these wafers a new gas inlet has been designed, from which tests have shown that a homogenous growth profile can be achieved

***Objective 2: Expand the limits in ON resistance of low ohmic power transistors (Workpackage 2)
Expand the limits in ON resistance of low ohmic power transistors in the 30V-50V range by introduction of enhanced Si substrate materials based on 300 mm wafer diameter. The step will enhance the existing 300mm pilot lines @Infineon.
-Work performed and main results achieved towards Objective 2:
WP2 has started successfully and is on track. In short time Siltronic had first 300mm crystals and sample wafers with ultra-low resistance as well as low oxygen defect optimized substrates available, achieving the two major milestones for the M06 period. A third milestone on the principal functionality of a boron counterdoping approach for the low oxygen defect optimized substrate could be also achieved in time. The first 300 mm sample wafers have been delivered to the partners for processing and further in-depth characterization. The respective special characterization methods like Microwave Detected Photoconductivity (MDP)- or Hall- measurements have been set-up and first sample measurements are ongoing or have been done by the partners FhG-EMFT, FhG-THM and Uni Oslo (Objective 1). First wafers on several IGBT- and SFET- technologies have been run at the device partner IFAT and IFD. Incoming inspection on wafer base and breakdown voltage evaluation looks promising and the wafers have been transferred to the device processing line. Some heads-up is coming from partner IFD towards slip line formation after thermal processing for the ultra-low resistance substrate. Also first characterization results from partly processed wafers are already available (Objective 2). In regards to the 300mm automation objective (Objective 3) all activities to enhance the automation capability flanked by new technologies for simulation of the material flow have been started. A first deliverable on a market survey of available FOUP transportation systems, their performances and the down-selection for the real case in the IFD fab have been achieved in time. Another focus is the fab simulation model of TUDr which now includes extended layouts of transportation with tools and uses an improved logic for more flexibility and better runtime performance. Several R&D activities were started between IFD and TUDr to detect critical vibrations or parameters during thin wafer transport. A FOUP was designed and equipped with an inertial measurement unit, which collects the box vibrations during the transportation. Another unit determines the resonance frequencies of the thin wafer inside the FOUP when the FOUP is shaken by single shocks. Finally, for the development of the smart-system performance monitoring – a self-learning background system, which has the purpose of analysing the variation in wafer transportation and handling – all suitable data sources and inputs were identified and the respective milestone M2.4 was achieved successfully

***Objective 3: Provide reliability test methodologies and analysis tools for novel GaN power switches on advanced carrier substrates in new 3D integration (Workpackage 6)
Provide reliability test methodologies and analysis tools for novel GaN power switches on advanced carrier substrates in new 3D integration and identify the new material specific failure modes and mechanisms, and develop life time models, in order to permit production and shipment of reliable and cost-efficient products.
-Work performed and main results achieved towards Objective 3:
During the first year of activity, the partners of WP6 – Reliability have extensively worked towards the definition of methods for the investigation of the mechanisms that limit the performance and the reliability of power devices based on gallium nitride. With regard to Objective 6.1: Innovation in reliability methodology, in the initial phase of the year, the partners have cooperated towards the definition of a testplan, that has been adopted for reliability assessment. Each partner has defined the standard characterization/reliability methods, and shared them with the other members of the workpackage. Specific test structures have been defined by IFAT and imec; UOB, UNIPD and STUBA have designed and proposed new test structures that will be employed for the study of specific parasitic mechanisms, including the off-state leakage processes and the defect-related trapping mechanisms. Suitable test structures have been defined also for the analysis of the thermal and switching behavior of the devices (UOB and imec). KAI defined a distributed test architecture to be used for reliability life stress testing of GaN devices; this is based on a modular system concept, that separates control and data acquisition from the actual test circuit. A methodology for GaN HEMT and MISHEMT failure analysis has been developed by IWMH and UNIPD. UNIGRAZ has used data from previous stress tests to develop models for the study of drift and the calculation of efficient guard bands for the initial test measurements.
With regard to Objective 6.2: Parasitic effect characterization and modelling, STUBA, UOB, IFAT and UNIPD have prepared a number of experimental setups and defined the related methodologies for the analysis of the deep levels in GaN devices and test structures. UNIPD and IFAT have focused the attention on transient measurements, while UOB has performed substrate ramp tests. STUBA has performed C-DLTFS measurements on devices provided by IFAT. A round robin experiment was carried out in order to ensure the alignment between the stress conditions. The results of the round robin test demonstrate a good alignment among the experimental methods and procedures used by the partners. In addition, UNIPD has optimized experimental setups for the analysis of the buffer-related trapping processes. UOB has developed optical methods for the thermal characterization of the samples, while imec has defined a set of thermal test structures for the investigation of the self-heating behavior. These structures were included on the new maskset which was taped out at imec.
The Objective 6.3: Identification of failure modes and mechanisms on device- and wafer level was initially addressed through the definition of a plan (UNIPD), that specifies the accelerated tests to be carried out at wafer level. This plan includes high temperature reverse bias stress in off-conditions; on-state operation at maximum current; stress experiment under realistic operation, and will allow to investigate the degradation processes induced by accelerated stress conditions. Imec has improved and evaluated the reference GaN buffers and devices grown on regular silicon, since this will be the baseline process used for the fabrication of novel substrates. At imec, a procedure was implemented to evaluate the long term stability of the GaN buffers. The stability of the buffers was investigated by means of TDDB experiments and demonstrated that the buffers can withstand a very high voltage (higher than the rated bias) for a long time. Stress tests were carried out on devices with p-type gate, to demonstrate the existence of a time-dependent breakdown process (UNIPD).
The Objective 6.4: Identification of failure modes and mechanisms on package- and system level was addressed through the following steps: a) definition of a plan for package/system level stressing of the devices; b) development and evaluation of a Unclamped Inductive Switching (UIS) tester; c) evaluation of the electromechanical and thermomechanical effects (they will be numerically modelled and simulated at KAI using FEM to understand related failure mechanisms); d) analysis of the functionality of the UIS system and study of the operation of GaN HEMTs under reactive load switching (Nano and STUBA). In addition, UNIPD evaluated preliminarily the safe-operating limits of transistors with p-GaN gate, through the execution of step-stress experiments.

***Objective 4: Enable MtM solution for high variability (Workpackage 4+5)
Enable MtM solution for high variability in chip packaging by advanced packaging technologies.
-Work performed and main results achieved towards Objective 4:
After specification of the processes in the first six months, the focus in the second half year of the project was on setting up the core processes. This will pave the way for a seamless integration into pilot production lines. The outcome and status of the activities were reported in two deliverables (D4.1 and D4.2).
The tasks are categorized into three main objectives supported by a fourth objective, namely characterization. The main objectives are:
1. Innovative interconnects: High temperature and 3D interconnects
2. Molding process and 3D stacking technologies
Plasma processes for advanced packaging.

***Objective 5: Setup a pilot line for normally-on and normally-off GaN power devices (Workpackage 3)
Setup a pilot line for normally-on and normally-off GaN power devices including the GaN epitaxy and increase the wafer size in production to 200mm (using 150mm intermediate step to minimize risk).
-Work performed and main results achieved towards Objective 5:
All tasks have been performed according to plan. Main focus at IFAT was on the installation and setup of GaN epitaxy and process line for industrial volume manufacturing. A stable GaN MOVPE reactor run to run condition could be achieved by advanced reactor parts cleaning, in particular an in-situ chlorine clean was implemented. Metrology equipment and corresponding measurement routines were installed enabling complete GaN epitaxy characterization in a fully automated mode. A new defect density inspection system was acquired and coupled with an in-line scanning electron microscope for immediate defect classification. Finally, a base epitaxy process was developed reaching breakdown values of ~850V.
Advanced GaN epitaxy defect simulations with ab-initio approaches were carried out at MPIE. Main effort was on the hydrogenation process of native defects during growth as well as on subsequent release of hydrogen. A phase diagram in pressure-temperature space for hydrogen behaviour was derived. Furthermore, Ga-H bond density at dislocation cores was calculated as function of hydrogen chemical potential.
Defect characterization at FhG-IWMH was aligned and advanced defect analysis procedures were defined. Evaluation has been started whether acoustic GHz microscopy is applicable for detection of dicing defects occurring in brittle GaN-on-Si material system. Moreover, investigation of residual strain within the buffer stack by TEM-NBED (Transmission Electron Microscopy - Nano Beam Electron Diffraction) is in progress.
Equipment installation and setup of measurement routines for electrical process and device characterization was performed. Dynamic RDSon test system is available and attached to automated wafer prober as well as to package level test sockets. In-line control plan and PCM test program for all relevant parameters were established.
GaN-on-Si wafer handling procedures were established in IFAT's 6"" Si CMOS line. All unit processes were classified with respect to Ga cross-contamination risk and required measures were implemented to run GaN wafers without danger for Si technologies. Unit processes were integrated into complete process flow and first fully integrated lots were run through the line. First functional 600V normally-on GaN HEMT wafers were obtained.
A device concept for a RFP Schottky HEMT was elaborated and the corresponding manufacturing processes were set up. First integrated runs up to back-side were performed. Wafers from these runs were subjected to initial physical and electrical characterization showing promising functionality

***Objective 6: Enhance the compliance of GaN in standard packages and modules (Workpackage 5+4)
Enhance the compliance of GaN in standard packages and modules as well as a pilot line for system in package technology enabling also bond wire free chip embedding of GaN devices with enhanced thermal behavior.
- Work performed and main results achieved towards Objective 6:
As planned, the first objective 5.1 was finished after M12 with the result that embedding in mold compound is the fa
vourite solution and embedding in laminate is conceivable (application specific as well as for standard products). Work on line automation and metrology is started and ongoing. First simulation results available. Results from WP4 will be continuously introduced into WP5.

***Objective 7&8: Achieve benchmark size and significant improvement in energy management (Workpackage 7)
• Achieve benchmark size and power efficiency for the applications in the use cases defined
• Achieve significant improvement in energy management for selected smart power systems; by this step, a next generation of compact power electronics for efficient use of electrical energy will become technically and economically feasible.
-Work performed and main results achieved towards Objective 7&8:
A general review concerning GaN HEMTs has been carried out focusing on GaN power converters presented in the literature (PFC, DC/DC-stage, DC/AC-stage), the current commercially available devices and their characteristics. Based on this information and taking into account the specific requirements of the applications addressed in this WP, the specifications of the demonstrators to be built within the WP have been defined.
Based on these specifications and the first Powerbase GaN samples (received in M10), the demonstrators for LED-lighting, solar, battery charger and power supplies applications have been launched. In parallel to the design and the development of the demonstrators, the test boards to be used for benchmarking measurements have been specified.
In the case of the telecommunications application, the first rectifier prototype of 3kW (composed of a PFC stage and a LLC stage) based on pre-Powerbase GaN devices has been built. In this first prototype an efficiency improvement has been achieved but only in the PFC stage."

Progress beyond the state of the art and expected potential impact (including the socio-economic impact and the wider societal implications of the project so far)

"HIGHLIGHTS - Progress beyond the state of the art:

*** Workpackage 1:
All planned novel substrate types could be delivered and evaluated.
Successful imaging of threading dislocations and energy levels.
Defects and impurities were imaged along cross section with Cathode Luminescence and correlated nicely with Photo Luminescence.

*** Workpackage 2:
First red Phos doped wafer < 1,2 mOhmcm available on 300mm.
Low oxygen IGBT substrates with boron counter doping looks promising.

*** Workpackage 3:
Good volume capability achieved for epitaxy tool with new in-situ clean.
Fully processed normally-on wafers with all electric parameters on target.

*** Workpackage 4:
Specifications for further process development worked out and target flows for pilot lines #1 (IFAG) and #2 (ams) available.

*** Workpackage 5:
Embedding technology for pilot line (IFAG) chosen as planned after M12: focus will be on embedding in mold compound technology for GaN devices (but also other approaches will be studied).
Advanced optical sensor demonstrator defined (ams) with two options; target process and fallback solution.

*** Workpackage 6:
Cross-correlation of several techniques for deep-level investigation in GaN epitaxial materials and devices (first round robin like experiment in this field in Europe).

*** Workpackage 7:
First promising results with PowerBase samples in selected applications.

*** Workpackage 8:
Consortium Agreement signed by all partners before Grant Agreement.

The expected impact of PowerBase compared to the DoA remains basically unchanged after the first project year.

In the field of perception the GaN on silicon topic achieved additional attention by Googles “Little Box Challenge”. This was an open competition to build a (much) smaller power inverter, with a $1,000,000 prize. The task was to design and build a kW-scale inverter with the highest power density (at least 50 Watts per cubic inch).
This started a global race for the highest achievable power density of a 2kW DC/AC converter that survives 100h of operation in the lab. More than 1000 design teams worldwide registered and many submitted a proposal. 18 proposals were selected to deliver hardware. 13 teams disclosed their choice for semiconductor switches. 10 of them (including the winner team) have chosen GaN on Silicon devices. This shows again the superior properties of GaN for compact applications and the necessity of PowerBase to make these parts available in an industrial scale and in terms of industrial reliability and price expectations.
The interest in PowerBase is also reflected by the invitations for presenting the PowerBase project at notable conferences."
Record Number: 193691 / Last updated on: 2017-01-24
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