Community Research and Development Information Service - CORDIS

H2020

R2POWER300 Report Summary

Project ID: 653933
Funded under: H2020-EU.2.1.1.7.

Periodic Reporting for period 1 - R2POWER300 (Preparing R2 extension to 300mm for BCD Smart Power)

Reporting period: 2015-07-01 to 2016-06-30

Summary of the context and overall objectives of the project

R2POWER300 program, is committed to develop and manufacture a multi-KET Pilot Line setting the stages and preparatory for the future extension to 300mm of Fab facility located in Agrate Brianza (Italy) on Smart Power BCD Technology.

R2POWER300 impacts wide different market segment (Automotive, Healthcare, energy, Industrial,) however every where it's required an interface between the intelligence of an application (ex. uP, sensors, logic circuit) to the power actuator stages.

Today the Smart Power BCD products mass production is at 200mm and is composed by different BCD versions; BCD8s is the last version at 160nm 200mm wfs; BCD9s is the next evolution still at 200mm wafer and 110nm, while BCD10 will feature 90nm lithography 200mm wfs first, with the successive porting to 300mm wafers. BCD stands for Bipolar + CMOS + DMOS, and is an integrated smart power technology invented by ST in the mid ‘80s.

The 4 main pillars of R2POWER300 are WP1 - WP2 - WP3 - WP4, respectively representing:

- WP1 Technology Enablers: The goal is to prove BCD9 (110nm gate length) and BCD10 (90nm gate length) most critical technological steps portability to 300 mm, and define the main technical requirements for next generation power semiconductor relevant tools (200mm → 300 mm).
- WP2 Technology R&D: The goal is to define and develop a new Smart Power BCD Technology platform and enhance the competitiveness of Smart Power (i.e. BCD9 and BCD10).
- WP3 Packaging and 3D: The goal is to develop silver sintering die attach investigation + high density capacitors based on a new silicon approach (nano and micro structuring realizing pores having high aspect ratio).
- WP4 Applic&Techn demon. is focused on designing application demonstrator to assess the effectiveness of the technology outcomes, from WP1 WP2 WP3.

WP5 and WP6 are the Dissemination, Exploitation Standardization and Project management through all the WPs.

During the 1st year activities no main issues faced.

Work performed from the beginning of the project to the end of the period covered by the report and main results achieved so far

"WP1: high "k" material have been investigated. The activities started with a wide literature search producing a restricted list of 6 dielectrics, for each of them different thickness and thermal treatment have been evaluated yielding on time the D1.1.1.
ST and LPE cooperated to finalize the EPI layer and utilized LPE EPI reactor to define the main parameters: resistivity, thickness, thickness uniformity, crystallographic stress, contamination, cap layer thickness. met on time goals D1.2.1

WP2: definition of the New BCD Technology platforms specifications in terms of Design rules, Tentative Process flow and High Voltage device architecture. A first test pattern layout has been completed during this time frame and first diffusion lot has been started in the diffusion line to start the silicon development of the new platform.
Four main activities have been carried out to meet the objective:
1) Design rules definition and Reference Process flow identification
2) High Voltage Isolation and epitaxial layer specification: TCAD and silicon results
3) Test Pattern Design, Layout and Mask Order
4) Setting the Stage for High Voltage device reliability evaluation

D2.1.1 issued with 3 months delay. D2.1.1 goals met

WP3: silver sintering die attach activities realized by BESI consisted first in a literature search assessing the current knowledge about sinter tools, after that defined the process tool strategy for collective sintering. met D3.1.1
POLITO made a research on the state of the art of three dimensional thermal models. met D3.2.1
PICOSUN - UNIPISA - ST collaborated to define the process to realize PS ALD high value capacitors, in addition Picosun implemented the first ALD on ST silicon with pores at high aspect ratio. met D3.3.1

WP4: deviation occurred when ST BCD9 110nm identified DC-DC test chip was not anymore utilizable in R2POWER300 as applicator demonstrator, because of it became ST full custom design. This obliged to identify another test chip still in BCD9 to be proposed in Nanodesign; the new identified test chip in BCD9 110nm is named TR&D Spin and implement all the features to drive motors for a drone. this means that it is not fully tailored to a Dc-DC for the ECG Nanodesign specs, nevertheless, bypassing the section devoted to calculate the motor angle rotation, it can be used anyway as DC-DC. This variation obliged Nanadeisgn in redesigning their ECG (before tailored for the first ST test chip toward a different IC configuration). met on time D4.1.1.

WP5: Project Dissemination Plan prepared by IUNET. met on time D5.1.2

WP6: First Periodic Report done. met on time D6.2.1
PCA and Annex IPR on delay"

Progress beyond the state of the art and expected potential impact (including the socio-economic impact and the wider societal implications of the project so far)

R2POWER300 impact represents an important step for the Smart Power BCD technology roadmap evolution, allowing the porting from 200mm to 300mm wafers and involving strong European competence, employee involvement in Europe and last but not least, very consistent amount of billing; in fact, Smart Power BCD ICs represents a subset of the Analog Market segment analyzed by WSTS in its last report (June 2016) and showing a CAGR 2016-2019 = 3.0%. ST Smart Power BCD ICs technology in the period 2005-2015 CAGR performed better, that is 3.2%. In order to keep and further increase the CAGR advantage and billing, the investigation on 300mm Pilot Line is fundamental to be competitive, in wide spread of application market (Automotive, Healthcare, Industrial Energy).
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