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SeNaTe Report Summary

Project ID: 662338
Funded under: H2020-EU.

Periodic Reporting for period 1 - SeNaTe (Seven Nanometer Technology)

Reporting period: 2015-04-01 to 2016-03-31

Summary of the context and overall objectives of the project

The goal of the SeNaTe project is to enable European suppliers to develop tool capabilities for the next generation 7nm IC technology which will enable the industry to keep on Moore’s law projection and direction which presently aim at 7nm manufacturing in 2018. Some of the European suppliers like ASML, ASM, AMIL are already in a strong position in their domain and in order to keep the lead and to develop the relevant tools and processes for the new generation, they need to be supported by a technology platform where they can assess their capabilities. In other words, the SeNaTe project will aim at the demonstration of 7nm IC technology integration on real devices in the Advanced Patterning Center using the imec pilot line. Innovative device architecture will be used and a lithographic platform for EUV and immersion technology will be demonstrated as well as the application of advanced process (viz. deposition, etch, cleaning, plating, and planarization) and holistic metrology platforms, new materials and mask infrastructure. FEOL & BEOL modules will be developed and fully characterized with the different metrology to evaluate the best options for patterning and process steps, minimizing cost, increasing performance, limiting variability and supporting 7nm module readiness in accordance with the industry needs and the ITRS roadmap.

The goal of the lithography work package, and thereby the overriding objective for ASML, is the development of a lithographic platform for the 7nm technology node, a factor two better than current state of the art lithographic equipment. The results of the project will be compared to the current state of the art lithographic systems which are implemented in high volume manufacturing, i.e. immersion lithographic equipment with an NA of 1.35.
Objective of VDL ETG is the development and qualification of the equipped vacuum vessel for the EUV source. Furthermore, VDL ETG’s objective is to support ASML in the integration and qualification of the wafer stage and wafer handler subsystems.
For DEMCON the goal is to implement advanced control algorithms in test tooling to qualify (both during design and production) machine modules and their components.
Key goals of Zeiss SMT are the development of designs, manufacturing technologies and metrology techniques for future EUV projection lenses with 7nm resolution capability. The lens will be based on anamorphic imaging principles and will become a key module for future EUV exposure systems. Several project partners will supply support to reach these goals.
Fraunhofer IWS investigates EUV reflection coatings for optical systems focusing on stray light and layer stress reduction, and on advanced coating profiles.
IMS develops a manufacturing technology for X-large Diffractive Optical Elements planned for the measurement of the surface precision of X-large mirrors.
Fraunhofer IISB works for the extension of simulation models for the efficient and rigorous simulation of OPC (optical proximity correction) and design relevant patterns and will perform simulation studies on the impact of scanner and mask patterns on the imaging and OPC performance.

The main objective of the work package 3 on metrology platforms, which comprises five tasks, is to develop7nm metrology tools and holistic metrology methods that can effectively support imec’s 7nm process module developments by providing important and relevant information about critical structural dimensions, defects and process anomalies at both mask and wafer levels in a cost and time efficient manner.
The metrology requirement, specification and holistic protocols for 7nm node are defined in the first task. The objective of the second task is to develop high coverage metrology tools with focus on 7 nm node metrology performance aspects including resolution, accuracy, precision, throughput and cycle time that are able to support the 7nm node module integration and that can be part of an holistic metrology scheme.
In task 3.3 local coverage (i.e. low coverage) metrology tools are developed with focus on 7 nm node metrology performance aspects including resolution, accuracy, precision, throughput and cycle time that are able to support 7nm node module integration and that can be part of a holistic metrology scheme.
Development of new TEM metrology solutions as part of holistic metrology schemes with focus on 7nm node metrology performance, time-to-data and throughput and including improvements along the whole chain of sample preparation, basic instrument performance and automation, metrology-analysis and novel characterization techniques is the objective of task 3.4.
The last task of WP5 comprises optimization of sampling plans, precision, accuracy, throughput (TPT), cycle time and total measurements uncertainties (TMU) for full N7 integration holistic metrology optimization (feed-forward and backward loops) and design based inputs for offline recipe creation, modeling will be provided.

In work package 4 new process steps enabling 7nm technology by using innovative hardware either installed at imec or at the supplier site are developed and provided. The development of new processes will include multi-patterning schemes and different process options for Back End Of Line (BEOL) and Front End of Line (FEOL). After meeting initial specifications the integration of the developed process modules and materials will be performed in WP6.
Generating the required pattern dimensions and uniformity for FinFET architectures will require the use of multiple patterning techniques. These will include Self Aligned Quad Patterning (SAQP) and multiple Litho Etch techniques. The SAQP integration flow will use various core and spacer materials in diverse process sequences and combinations. 7nm BEOL interconnect will require new materials and integration techniques to deliver the required values for of line resistance, line to line capacitance and reliability. New dry etch processes for advanced patterning in BEOL are developed. New deposition techniques for N7 FEOL will be delivered based on ALD (Atomic Layer Deposition), CVD (Chemical Vapor Deposition) and electroplating. For Gate-all-around (GAA)-devices new materials and techniques will be developed. Finally, different new spin clean process will be developed including group IV semiconductor compatible critical cleans and passivation.

In work package 5 the objective of the first task is to study and to reduce EUV induced contamination and degradation on mask (+ pellicle). For this purpose TNO builds a dedicated electron beam line (EBL 2) research tool with access capability for full masks, to study such effects at EUV source power beyond that available on today’s EUV scanners.
Task 5.2 deals with backside cleanliness. Its main target is to refine imec’s way of working for back-side particle avoidance for NXE3300 reticles, to avoid impact on printed overlay. This addition to the established capability is based on an integrated infrastructure for automated handling, cleaning and back-side inspection of EUV reticles realized through the Suss MaskTrackPro cleaner (MTP), equipped with the InSync automation module and SPARK back-side inspection.
The intention of task 5.3 is absorber material optimization. Significant pitch-dependent effects on wafer level have been reported, caused by the interaction between non-perpendicular light incidence and absorber pattern, i.e., so-called mask 3D (M3D) effects. These need to be overcome by an alternative absorber.
The objective of task 5.4 is to work out pellicle solutions for EUV lithography, including the development of i) alternative pellicle membrane materials, ii) infrastructure for maintenance of reticles with pellicles and iii) automated pellicle mounting tool.
Objective of Task 5.5 is to demonstrate a defect-free EUV reticle using different defect mitigation techniques, such as multi-layer mirror (ML) defect compensation repair and pattern-shift. In particular the target is to have no residual printing ML defects on wafer level.
The intention in task 5.6 is to bring particle contamination on the pattern side under control during handling, transport and use for exposure in the scanner, in addition to applying a pellicle (topic of task 5.4), and while becoming compatible with the latter. For this purpose a high sensitivity particle scanner with dedicated handler is under development by TNO. Cleanliness assessment tests are planned with and without pellicle, during transport, handling and use for exposure in the scanner.

In work package 6 the new process platforms (new processes, new materials, new equipment modules) developed in work package 4 will be implemented in FEOL (Front End of Line), MOL (Middle of Line), and BEOL (Back End of Line) modules in order to assess the different process options fulfilling for 7nm technology design rules, performance, power, area and cost specifications.
The work comprises five main tasks. The first task, 6.1, encompasses the definition of the design rules and the assessment of the different patterning options identified after the finalization of the design rules. Task 6.2 and task 6.3 deal with the implementation and validation of the critical processes in the respective FEOL, MOL and BEOL modules. Task 6.4 concerns the evaluation of different strategies to boost the device performance either by introducing new substrates (SOI), new device architectures (gate all around) and/or replacing the Si channel with high mobility materials. The last task, 6.5 addresses the full integration and electrical testing of the best options for the 7nm technology selected from the preceding tasks.
A strong interaction with the other work packages: WP2 (EUV lithography platforms), WP3 (metrology platforms), WP4 (process platforms), and WP5 (EUV mask maturity) is key for a successful execution of the tasks listed under work package 6.

Work performed from the beginning of the project to the end of the period covered by the report and main results achieved so far

ASML activities concentrate on the integration of all large subsystems and of the 1st EUV lithographic system for the 7nm technology node. By the end of the reporting period the integration of the large subsystems is nearly finished apart from the optical system, which logically comes as the last subsystem. The full system integration also progresses well; several systems are integrated in parallel. The first, a test system with an optical system from the previous family, is nearly completed. Following these integration activities the functional and performance qualification can commence.
DEMCON designed and realized two qualification tools based on different architectures: one for the Mk5 positioning module, the other for short-stroke actuators of the wafer stage. Currently, DEMCON is in the process of validating the qualification tool performance.
At VDL ETG, an initial series of vacuum subsystems for the EUV source is integrated and qualified functionally. A first prototype of a new model has been integrated and functionally qualified.
Based on a comprehensive study Zeiss has made a design decision for future lenses with 7nm resolution capability. The lens will be based on an anamorphic imaging approach. The top level specifications are defined. Furthermore, Zeiss has started with the development of lens manufacturing technologies and preparation of the appropriate metrology techniques.
HQS experimentally demonstrated the feasibility of decreasing the slope of the coefficient of thermal expansion and thereby increased the ‘close-to-zero expansion’ temperature range by co-doping a titania-doped fused silica glass. From these results a useful range for the required dopant concentrations could be derived. This will be the base for future continuation of these efforts.
The major results of Fraunhofer IWS are a reduction of layer roughness, an improvement of the stress uniformity on strongly curved substrate surfaces, and an extension of the deposition technique for the fabrication of free-form thickness profiles to substrates with 200 mm diameter.
IMS has finalized the equipment choice for the setup of a development and manufacturing line for X-large DOEs. First long-term exposure experiments on the e-beam exposure system are performed to simulate the printing process for X-large DOEs. This will be the base for future system and process improvements.
Fraunhofer IISB has continued with the extension of the simulation models. The prototype of the implementation of isolated boundary conditions for the waveguide method was tested and verified for additional use-cases. Concepts for the implementation of a decomposition technique were studied. Furthermore, the simulation work has been done focusing on the modeling of Jones pupils and related polarization effects in higher NA EUV systems.

The work progressed across all the metrology and defectivity tools activities which are described in the Annex-1. The results comprise:
specifications and requirements list based on 7nm process modeling, 7nm virtual process model to a reference metrology (TEM) calibration activities, optical path enhancement to optical defectivity tools, optical critical dimension prototypes testing based on simulations, high efficiency FIB and high resolution TEM modules tested, CDSEM application development for accuracy and 3D profiling tests showing to improve the baseline by 50% , SPM (scanning probe microscope) tip exchange tests ending successfully, progress of fast E-beam platforms and modules for inspection and review toward better resolution and throughput and preparation of a setup for bulk stress measurement.
Holistic metrology task advanced as well with work related to E-beam, SPM, TEM and modeling (E-beam effect on low k materials and reference metrology calibrations).

The main work performed in the first period of the SeNaTe project within WP4 can be summarized as follows:
‐ Install different process platforms at imec and make them available to perform process development for 7nm
‐ Develop films and processes for hard mask (FEOL and BEOL) and CD shrinkage
‐ Develop films and processes for low k dielectric, barrier, Cu fill and Cu CMP and meet initial specifications
‐ Initiate development of materials and processes for GAA
‐ Develop first processes for spacer and core layers for integration
‐ Develop initial deposition processes for FEOL materials based on ALD and CVD
‐ Conduct a cost analysis for SAQP patterning and select different patterning schemes
‐ Define target specifications for CD, CD uniformity, line edge roughness, profiles and depths/heights and deliver unit-processes for the different SAQP sub-steps
‐ Develop initial dielectric barrier and selective Co capping
‐ Initiate development of BEOL etch and clean as well as electroplating
‐ Specify and develop single wafer cleaning for FEOL/MOL based on flying wafer concept
‐ Conduct process modelling to validate and support patterning schemes and provide process specifications for several cases

In task 5.1 good progress is made with the development of the dedicated EUV Beam Line (EBL2) tool by TNO. On this tool it will be made possible to vary several process parameters around what they will be for later versions of the ASML NXE scanner with production oriented source power. Meanwhile the detailed design has been completed. The procurement of hardware is now in progress and the equipment is expected to be operational by Q1/2017.
Since the completion of the installation and site acceptance of the NXE3300 at imec in summer 2015, imec runs monitor exposures as to track stability of printed CD over time. The cumulative dose that the reticle received so far is still low relative to target production needs. The high level conclusion at present is that contamination/deterioration of this monitor mask is at most negligible. At higher source power this will need to be reconfirmed, exactly what is intended as experimental work on EBL2.
In task 5.2 the in-situ Reticle Backside Inspection module (RBI) of the NXE3300 was taken into use, and embedded into the updated way of working for back-side particle avoidance. Good correspondence to the SPARK was found, even quantitatively. RBI automated reject could be successfully implemented.
The work started in task 5.3 with refining modeling of the current Ta-based absorber based on experimentally obtained optical properties, layer thickness and pattern profile, on the mask, together with exposure results obtained on the NXE3300 lithographic tool. A first selection of alternative absorber materials is made based on their imaging potential (based on reported optical properties at EUV wavelength) and processing capabilities on wafer among the partners. The thickness of the selected materials was optimized through simulation by minimizing M3D imaging effects and found to be significantly thinner than the current Ta-absorber of 70nm. Good experimental progress is made with Ni films on wafer, and intended demonstration will be using the actinic metrology capabilities among the partners.
Within task 5.4 imec and ASML are working in a complimentary way on the development of an alternative material for the pellicle membrane using different approaches. Included in these are:
‐ Carbon Nanomaterials (CNM) (imec)
‐ Porous membranes, created with DSA-patterned etch (imec)
‐ Graphene (ASML)
‐ SiN (ASML) as alternative membrane films
‐ UTwente works on the development of cap materials that could be applied to all four options above.
In parallel, there has been work on mask infrastructure:
‐ Suss has worked on enabling the MaskTrackPro cluster at imec to handle reticles with pellicle attached and clean these reticles. The required tool modifications and the technology requirements have been defined.
‐ HAP has evaluated existing handling systems relative to their suitability and possible restrictions for pellicle use. Essential targets to enable automated mounting of a full-field pellicle for use on EUV lithographic scanners have been defined.
Process development and demonstration of repair capability for EUV mask started in task 5.5. For exploration of mask defect mitigation a test mask with 22-16nm hp design was manufactured, inspected and printed on wafer. Matching several available defect maps (mask blank, patterned mask, printed wafer) provides a test vehicle to find all so-called multilayer (ML) defects for further study of ML compensational repair. Exploration and development of a so called pattern-shift process which places the design on the mask in such way that critical ML defects will be covered by absorber or shifted into uncritical areas of the design has started. Simulation was setup to predict the placement accuracy of the pattern-shift process and pattern-shift functionality installed on the e-beam writer. Fiducial marks on the mask blank will serve as anchor points for defect maps and e-beam writer to place the design on the desired location. First experiments to study influence of fiducial marks geometry and quality on e-beam alignment started. As next step an experimental plan was setup to explore final alignment accuracy of the e-beam writer to the ML defect locations by superimposing a marking pattern, such as frame, onto the typically used equal l/s patterns.
According to plan the design for the development of the particle scanner is finished in task 5.6, parts are manufactured and the assembly is ongoing. Also for the development of the handler robot the requirements are agreed on and the development is ongoing. For the evaluation of particle adders on the reticle quality side during use for exposure, still without pellicle, first tests are performed on the NXE3300 tool using pre – and post cycling exposures, showing zero adders within the applied detection limit.

In reporting period 1 the design style assessment - unidirectional versus bidirectional - for standard and SRAM cells was completed resulting in design rules and process assumptions. Regarding the process options, both 193i multiple patterning and single exposure EUV patterning solutions are identified. It is believed, because of the strongly reduced process complexity, that EUV can result into a more cost effective technology.
The key activities during the first reporting period comprise: 193i multiple patterning options assessment, EUV single exposure patterning assessment, development of metallization processes for 16nm L/S metal lines, and optimization of process steps for fin module integration.
For fin the 193i based Self Aligned Quadruple Patterning (SAQP) yielded 8.5nm fins @22.5nm pitch. The optimized process yields CDU, LWR, LER and pitch walking performance meets the 7nm node technology requirements. For 16nm line/space metal 1 also a 193i SAQP based multiple patterning process was successfully developed. Furthermore, the 16nm line/space grating patterns were successfully metalized using CVD Mn/Ru liner/barrier technology and Cu plating
Regarding the exploration of EUV based single exposure options for 7nm technology in reporting period 1, a new mask set (PLUTO) exploring both 1D and 2D process options has been designed. Reticles are delivered to imec in Q1/2016. Explorative work yielded the selection of new EUV photo resist for L/S applications, and a metal containing resist for the block application.
For fin module integration, process step optimization including trench filling, film densification, CMP and recess etch was completed. It was found to be essential to reduce the thermal budget during the different annealing and film densification process steps.
The FEOL module integration using the newly designed ATR70 mask set was started. Fin and gate module integration are worked on in parallel.

Progress beyond the state of the art and expected potential impact (including the socio-economic impact and the wider societal implications of the project so far)

All results mentioned in section B are beyond state-of-the-art. An example is given below:
ASML and VDL ETG were able to integrate and qualify advanced novel systems for Sn management in the EUV source. The expected impact is better source availability and higher output power levels.
The various metrology modules and tools which are developed in the project will enable higher throughput, precision and accuracy level of critical measurements in the 7nm process flow and will improve both the monitoring and process correction feedback flows.
The final performance of those innovations will be assessed by an end user, Intel. The feedback from this industrial player will open the door for further adjustments as found to be required in preparation for high volume manufacturing.
AMBEL developed new films and processes for N7 hard mask and CD shrinkage, for low k dielectric, barrier, Cu fill and Cu CMP. ASM-B’s R&D concerned the development of 7nm deposition processes for spacer and core layers as well as other 7nm FEOL materials based on ALD and CVD. LAM-B studied different patterning schemes for SAQP, developed initial dielectric barrier and selective Co capping.
A virtual fabrication flow based on Coventor’s software is employed to capture and develop processes, and to evaluate different process options. Specific efforts were undertaken with LAM-B to evaluate different patterning schemes for Fins.
Imec collaborated with all WP4 partners to ensure the availability of the required processes in imec’s 7nm pilot line. The majority of developed hardware and processes are expected to be employed in future 7nm fabrication.
TNO had previously built the EBL1 to support the development of the NXE scanner itself by ASML and Zeiss. Apart from higher source power, the major add-on is the accessibility with a full reticle, in a way that it will keep meeting cleanliness requirements to allow printing based evaluation of scanner of the mask “treatments” made. Therefore, the targeted impact is a better understanding of mask (+ pellicle) degradation at source power levels typical for high volume manufacturing EUV lithography, based on local “treatment” of the mask using the dedicated beam-line facility, supplemented with mask performance evaluation via wafer printing and mask metrology.
Since RBI (an option for NXE3300) is implemented there has not been a need for a reticle clamp clean on the imec NXE tool. It is found to be a major asset to keep the risk of overlay critical back-side particles on NXE reticles low. Any time a reticle is loaded into the scanner or comes back from the reticle stage it is measured and inactivated when the backside cleanliness requirement is not met.
The need for an alternative absorber material on EUV masks has been expressed by the industry. However, experimental research into alternative absorber materials has been limited because there is no involvement of the blank supply chain as there is no immediate return-on-investment expected.
The project goal is to demonstrate experimentally – on wafer samples – the reduction of M3D effects for current and future industry nodes by changing the absorber stack of the EUV mask. Therefore, the intended impact is to convince the blank supply chain to make the selected absorber material commercially available.
The current state of the art pellicle membranes are viable only to EUV exposure powers of less than ~80W and the industry infrastructure is in early stages of development. The project activities focus on power levels of ~250W and systems are developed to support manufacturing. Consequently, all activities in WP5 are beyond state of the art. The expected impact is an addition to the EUV mask infrastructure for a reticle with a pellicle and a pellicle membrane material fulfilling HVM requirements.
Whereas some aspects of ML (multi-layer) defect mitigation are published already, reporting feasibility of ML defect compensation repair for nodes >7nm and of pattern-shift, the WP5 project activities intend to refine this into a complete process flow by assuring:
‐ Full proof blank inspection (i.e. with all printable ML-defects pre-detected on blank),
‐ Learning on repair capability and limitations,
‐ Pattern shift with tighter alignment capability, ideally within half of the pattern pitch
‐ Development of an overall defect mitigation scheme for implementation into 7nm EUV mask manufacturing.
The expected impact is a higher success rate of reaching defect free reticles, effectively based on what would print, and not limited by insufficient knowledge of blank defects present.
Near future EUV equipment requires cleanliness at a particle size above 20nm. State-of-the-art reticle handling equipment is typically qualified for particle sizes from ~60nm onwards. Measuring and assuring clean handling of reticles at 20nm particle size is extremely challenging. Using a pellicle on the EUV reticle, intended to keep particles out of focus during imaging, is one of the required steps. However, handling/measuring equipment must also perform at this particle size level and a solution with the additional pellicle present is required. The industry will benefit from the developed infrastructure through the availability of clean handling and measuring equipment for cleanliness at 20nm particles. This supports EUVL towards a solution for pattern side particles.
In the first reporting period the consortium members have demonstrated that within the consortium all the competences (knowledge, advanced processes, design, next generation equipment) is available to produce in silicon devices which meet the morphological specifications for future 7nm node technology. In period two the patterning options evaluations will be completed identifying the economical most favorable process integrations paths. Advanced process steps developed during the first 12 months will be merged to build FEOL, MOL and BEOL modules which in year three will allow for the electrical demonstration of 7nm technology node devices.
Achievements from the first reporting period underline that European industry and R&D institutes continue to take up a forerunner role in the semiconductor industry.

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