Community Research and Development Information Service - CORDIS


WAYTOGO FAST Report Summary

Project ID: 662175
Funded under: H2020-EU.

Periodic Reporting for period 1 - WAYTOGO FAST (Which Architecture Yields Two Other Generations Of Fully depleted Advanced Substrate and Technologies)

Reporting period: 2015-05-01 to 2016-07-31

Summary of the context and overall objectives of the project

The project objectives have been precised in the technical annex of the amendment submitted in September 2016.

The overarching goal of WAYTOGO FAST remains unchanged; it is to provide, thanks to an industrial European consortium covering the full value chain, a sustainable route to FDSOI technology for future CMOS nodes and maintain the European industry leadership in equipment, metrology, materials and IP/Design on this alternative More Moore technology.
WAYTOGO FAST targeted products aims to open a sustainable route to FDSOI technology by extending the scope of the 28nm node and supporting the 22/22+ nm nodes.

For ST-Crolles, starting January 1st 2016, the developments will aim at qualifying a pilot line for the extensions of the 28-FD SOI platforms:
• Ultra-Low Power / Ultra Low Voltage 28 FD-SOI
• Compatibility of the CMOS process with the eNVM option
• RF 28 FD-SOI
• Hardened 28 FD-SOI for automotive, and space respectively

SOITEC will manufacture the innovative substrates to provide sufficient samplings to ST and Global Foundries and these manufacturing lines will process the hundreds of individual processing steps constituting the FDSOI technology.

In the first 8 months of the project, the development focused on the 14 FD-SOI and the preparation of the 14+ FD-SOI with the development and validation of specific booster for the device. In the second part of the reporting period, as ST held the development of the 14 FD_SOI, the work within WayToGo Fast has been redirected for the ST Crolles pilot line, towards the extension of the scope of the 28 FD-SOI.
SOITEC continued to work on the advanced substrates to support the pilot line of ST Crolles and the 22 FDX technology of GlobalFoundries, also investigating in ultra-thin BOX processes and alternative SOI preparation.

As of end of July 2016, the work is progressing well and the objective of having the 2 pilot lines operational at the end of the project is on its way.

Work performed from the beginning of the project to the end of the period covered by the report and main results achieved so far

"The work is progressing in the different work packages as described in the technical report. The technical achievements of the main partners are described below.

1,3 ST Crolles
First results on the process and device feasibility for 14FD+ devices have been obtained. The starting point for the analysis can be found in the guidelines detailed in deliverables D1.2.1.2 (Report on FEOL process module requirement to achieve 14FD+ transistor), D1.2.1.3 (FEOL process modules for 14FD+ technology), D3.2.2.0 (14FD+ Device Specification) and D3.2.3.0 (14FD+ Process and Device Feasibility Report). Advanced Device Characterisation activities are reported in Deliverable D3.2.6.0.

Concerning the pilot line for the 28 FD-SOI extension, different performance boosters explored in WP1 have been identified as possible options for the new Ultra Low Voltage devices under development. We have investigated with the available technologies (process, tools,…) the following items : ultrathin BOX, solutions for tensile stress (sSOI, STRASS), solutions for introducing more compressive strain into the channel of pFETs (BOX creep). Performance boosters developed for the 14FDSOI and the 14FD+ have started to be reengineered to be applied to the 28FDSOI Derivatives : the gate stack change : from HfSiON to HfO2, the dual workfunction gate metals, the SiGe channel for the PMOS, the Low k spacers integration.

During the first period of the project CEA LETI worked in close cooperation with ST on the required process modules for 14FD+ and for monolithic 3D integration have been investigated. A specific focus has been put on innovative techniques allowing to introduce local strain and on high mobility channel as well.
A second axes of CEA LETI work was done in cooperation with SOITEC on the SOI substrate development. Two high mobility materials have been studied: strained silicon (sSi) and silicon-germanium alloy with high content of Ge (Si0.3Ge0.7). For both materials the donor wafer development is of prime importance. Concerning sSi material, we have characterized the donor substrate (Si0.8Ge0.2) and developed the 300 mm sSi epitaxial growth. On Si0.3Ge0.7 material, we have characterized the donor substrate (Si0.3Ge0.7) delivered by Siltronic, developed the 300 mm SiGe epitaxial growths needed for our integration scheme and fabricated the first 300 mm SiGeOI substrate. We have developed a simple and efficient route for fabricating electrical tests vehicles, called Smart Pseudo MOS (SPM) devices, the concept is to fabricate Pseudo MOS structures that can be tested as easily as regular MOSFET. To do so, we used a CEA LETI MOSFET route (up to Metal 1, 65nm design rules) in which we consider the following bricks: SOI, Active areas definition (litho, etching, stripping), Back end (Contacts, Metal 1)

5- Soitec
Soitec leads the "Development and pathfinding of advanced substrates" work package (WP2) and integrates the developed technologies building blocks in its advanced substrates pilot line (WP3 / Task 1).
Within this first period, 2 new substrates were developed and characterized for the next technology node: sSOI (strained SOI) and Si0.3Ge0.7OI. The realization of these first prototypes included an in depth study and work on each of the SOI fabrication process steps. This work was performed in strong collaboration with Siltronic and CEA-Leti. These 2 prototypes were then deeply characterized with the support of INPG and CEA-Leti. The conclusion was that SiGeOI alternative could not match the surface quality requirements for the next node and would require much more important developments to close the technical gaps on crystalline defectivity. The sSOI remains a strong potential solution for the next technology node (12FDX).
In the meantime an important work with EVG and DSD in particular was performed to increase equipment capabilities. EVG bonding tool was transformed to include a plasma activation module with the target to increase the overall bonding / splitting process yield. DSD single wafer cleaner was transformed to support the developments done at Leti and Soitec concerning the cleaning of Si, sSi, and SiGe as well as the selective etching of these materials.
These developments on material, process and equipments (WP2) were mostly implemented in the substrate pilot line (WP3, task 1) which aims to produce SOI substrates in full compliance with the 22FDX technology and anticipate the next node requirements.
Within the first period, the targeted substrates specification were defined in collaboration with GF, the implementation of the pilot line was realized with a completion rate of 90% of the process and tools, the control plan is in place on the pilot line thanks to a great work performed on HSEB alpha tool and many other metrologies, the sampling of first prototypes was achieved above the initial plan with a yield improvement and a learning curve at the expectation level, and the evaluation of the substrates on first devices could be performed by our partners (GF)."

Progress beyond the state of the art and expected potential impact (including the socio-economic impact and the wider societal implications of the project so far)

The work is progressing in the different work packages as described in the technical report. The progress beyond the state of the art and of the socio-economic impact will be provided with moredetails at the end of the project.
Record Number: 196500 / Last updated on: 2017-03-29