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RESCUE Report Summary

Project ID: 648635
Funded under: H2020-EU.1.1.

Periodic Reporting for period 1 - RESCUE (REsistive-Switch CompUting bEyond CMOS)

Reporting period: 2015-08-01 to 2017-01-31

Summary of the context and overall objectives of the project

The age of information relies on the scaling of CMOS technology, which allows the decrease of cost per component, and the improve of computing performance at each technology generation. However, CMOS scaling is slowing down due to inherent physical scaling problems, such as the short channel effects which raise the static power consumption and does not allow the downscaling of the dynamic power consumption. In addition, the transfer of data between the memory and the central processing unit (CPU) introduces a ‘memory wall’ issue, in terms of latency and additional power consumption. All these problems can be solved by novel in-memory computing architectures, which would totally suppress the memory wall and the static power consumption by using non-volatile switches for computing. A novel computer based on this concept would revolutionize the scenario of computing by enabling ultra-high density, ultra-low power logic and analog processors for several applications, from the Internet of Things (IoT), to neuromorphic processors for artificial intelligence.
This project aims at the development and demonstration of a new computer using resistive switch devices for computation and memory within an in-memory computing architecture. The project will address this broad objective from different standpoints, including (i) developing a novel generation of resistive switches with improved window and cycling endurance capability, (ii) develop a novel resistive-switch logic architecture serving as a universal platform for in-memory computing, and (iii) developing novel schemes for analog computing, including brain-inspired neuromorphic computing, by using resistive-switch technology.
Achieving these goals would result in a paradigm shift for the electronic industry and for society, by introducing a scalable technology of devices serving as both switches and memory, thus serving all in-memory applications in both the digital computers and analog systems, such as the neuromorphic networks for object learning and inference. For instance, the availability of non-volatile logic computing schemes will enable low-power microcomputers for the IoT, where event-driven computation takes place only in correspondence of sensory inputs. Massive in-memory computing architectures using digital/analog resistive switches would allow efficient processing of big data problems, such as data clustering and hardware learning accelerators. Analog neuromorphic systems with nanoscaled synapses will enable brain-inspired computation in robots and drones, and allow for low-power, high energy-efficient driverless cars.

Work performed from the beginning of the project to the end of the period covered by the report and main results achieved so far

During the first reporting period, the execution of the project has been successful and overall on time. The project is organized into 3 main activities: (i) development of a novel generation of resistive switches with improved window and cycling endurance capability, (ii) development of a novel resistive-switch logic gates serving as a universal platform for in-memory computing, and (iii) development of novel architectures for resistive switch computing, including memristive logic and neuromorphic computing with resistive synapses.
Within this framework, the achievements of the project during the first reporting period are the following:
1) We developed a new technology of high performance digital/analog switches, consisting of a stack of Ti electrodes, SiOx dielectric layer, and C bottom electrode. These devices have shown outstanding resistance window (about 1E4 between on and off states), high endurance (above 1E8 cycles) and good retention at high temperature (at least 1 hour at 260°C). Replacing the top electrode with Ag results in volatile devices, with retention in the microsecond range, and on/off ratio exceeding 1E7. These devices are currently being extensively deployed to demonstrate novel resistive logic circuits and neural networks.
2) We explored alternative resistive switch technologies to be brought on board of the project for best performance. To this purpose, we studied resistive switches consisting of spin-transfer torque (STT) random access memories (STT-RAM), which are relevant for in-memory logic and RNG. A high endurance, approaching 1E11, was experimentally evidenced and explained by the electronic state switching in the STT-RAM and by the time-dependent dielectric breakdown in the active MgO layer These results are extremely promising for the implementation of RNGs and logic gates with a STT-RAM technology platform.
3) We developed novel RNG circuits based on differential pairs of resistive switches, capable of generating streams of random numbers without any need for calibrating the applied voltage. The random number is generated based on random set and random reset, where the randomly-variable switching parameters of the 2 switches (e.g., the resistance value, or the set voltage) are compared during an applied voltage pulse. We are currently developing improved schemes for RNG, employing STT-RAM and taking advantage of the higher endurance and faster switching of the device.
4) We have developed a new synapse for spike-timing dependent plasticity (STDP) based on a one-transistor/one-resistor (1T1R) structure. The learning and recognition capability was demonstrated by simulation of a 28x28 neuron network.
5) We have designed, fabricated, and tested a new hardware for neuromorphic computing using resistive switches. The hardware consists of a 2-layer perceptron with up to 16 pre-synaptic neurons and 2 post-synaptic neurons. The hardware allows to directly demonstrate brain-inspired computing using resistive switches, e.g., the neuromorphic hardware is capable of learning and recognizing patterns, tracking patterns, and specializing to individual patterns by winner-take-all algorithms. Overall, this is the first full-hardware demonstration of unsupervised pattern learning with resistive switch synapses. We look forward to use the same hardware as a flexible platform for designing/testing other innovative in-memory computing schemes.

Progress beyond the state of the art and expected potential impact (including the socio-economic impact and the wider societal implications of the project so far)

In-memory computing is currently a research topic of many academic and industrial labs, because of its potentially ground-breaking impact on computing systems in applications covering the whole spectrum from consumer, to IoT and big data problems. Today, portable computer are plagued by excessive power consumption, excessive latency between CPU and memory, and inadequacy to solve inference problems, such as learning and adapting to sensory information. All these limitations may be disrupted by the introduction of a new computing technology in terms of new device switches, new architectures, and new operation schemes. The project RESCUE addresses all these aspects in a holistic approach to co-design in-memory computing solutions.
The novel device technology based on SiOx switching shows outstanding performance in terms of resistance window, cycling endurance, and retention. Memory industry already manifested interest in possible exploitation of this technology, given the added value of SiOx being a highly CMOS compatible material, known from decades for its use in the process lines of the microelectronic industry. At first, we plan to encourage the deployment of this novel technology as embedded memory in system-on-chip (SoC) solutions, such as microcontrollers, power chips (e.g., STM BCD9) and IoT hardware. The embedded memory can serve as first niche application for making industries familiar with this technology, and prepare the ground for later, long-term introduction of in-memory computing systems, such as neuromorphic processors or machine learning chips.
The innovative RNG scheme that was developed in the project promises to have a ground-breaking impact on IoT for several applications, ranging from data encryption to physical unclonable functions (PUF), for hardware signature to avoid chip/identity counterfeiting. Our resistive-switch RNG passed all standard (NIST) tests without any external post-processing of data, which is generally hard to achieve, especially with stochastic devices such as the resistive switch. The high functionality is balanced with an extremely small cost in terms of occupied area and power consumption. Another advantage is that RNG and embedded memory would share the same device technology, which agrees well with the in-memory computing philosophy. Therefore we expect this innovative RNG to gain attention as a low-cost, highly efficient machine for generating random numbers in a variety of application scenarios. We are currently planning to boost the transfer of these technologies to industrial platforms by developing integrated demonstrators and assessing the market opportunities to set the stage for exploitation strategies, in the form of IP protection, IP licensing and company creation.

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