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AVHDL development environment for reusable VHDL descriptions

Virtual hardware description language (VHDL)-integrated common environment (ICE) is a VHDL development environment for design teams working on multiple versions of reusable VHDL descriptions. Built for heterogeneous computing environments, VHDL-ICE helps VHDL development teams build virtual components in a reliable, reproducible way. It also allows VHDL developers to address previously intractable problems in the management of intellectual property rights.

VHDL-ICE's advanced capabilities directly address previously intractable problems in the management of Intellectual Property Rights (IPR) for VHDL development teams. Current VHDL-based design methodologies include developing and maintaining multiple virtual components( VC) concurrently, guaranteeing the accuracy of product releases, re-building previously-shipped or acquired VHDL VCs enforcing uniform development policies, and handling requests for technology releases. By solving these problems, VHDL-ICE helps VHDL development teams build all of their VCs reliably, in a reproducible way, without error. The first stage of VHDL-ICE provides facilities for teamwork, organization and workspace management, including management, navigation and assessment facilities for VHDL VCs, without forcing VHDL developers to change their development tools or the way they work. The second stage of VHDL-ICE includes version control and configuration management. Eventually, VHDL-ICE will be enhanced to support design methodology management and process control.

Contact

Serafin OLCOZ
Tél.: +34-91-8043914
Fax: +34-91-8044551
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