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Fabrication and architecture of single electron memories

Exploitable results

The minimum feature size in the three main semiconductor memory devices, DRAM, SRAM and non-volatile, is projected to reach about 50 nm by 2012, after which new memory devices are expected to be introduced, for both technological and economic reasons. The FASEM consortium has invented a possible replacement technology, the Lateral Single-Electron Memory (L-SEM). Single-electron memories have several advantages over conventional memories: low power consumption, longer storage time than DRAM, and faster access time than current non-volatile memories. The L-SEM can be used to fabricate a fast, random-access memory with the potential for large-scale integration. The project has been successful in showing that single-electron transistors can be the basis of a CMOS-compatible memory technology for the terabit era. The fabrication of nanostructures for these devices has advanced the state-of-the-art significantly, and small L-SEM memory arrays have been linked to peripheral devices in a CMOS circuit, establishing the compatibility of L-SEM processing with standard CMOS processing. The L-SEM cell uses a single-electron device coupled to a conventional MOSFET. The cell has been fabricated in crystalline silicon-on-insulator (SOI) material using a heavily-doped, side-gated silicon nanowire single-electron transistor (SET). Typically, the SET silicon nanowire cross-sectional area is less than ~40 nm ? 40 nm. The cell has been operated with detectable storage of small electron numbers (~60 electrons on a 1 µm ? 70 nm area memory node). The write/erase time of the cell is 10 ns and the cell can operate successfully at temperatures up to circa 50 K. The crystalline silicon-on-insulator L-SEM cell has been integrated into a small 3 ? 3 bit memory array. Full functional operation of the memory has been demonstrated, including the read/write timing cycle and cell selection without data corruption. Potential barriers to the commercial application of the L-SEM array include: operating temperature (at present, operation has been demonstrated up to ~50 K, but higher temperatures approaching room temperature should be possible as the technology develops); storage time (currently 1 s at 40 K); competition from other non-volatile memories, like the PLEDM and FeRAM. Several years of further research and development are required before the technology can be considered by industry for prototyping.
In order to overcome limitations of conventional non-volatile and dynamic memory devices, it has been recently proposed to use nanocrystals as charge storage elements embedded in the gate oxide of a field-effect transistor (FET) and located in close proximity (2-3 nm) to the transistor channel. The use of ion implantation for the fabrication of nanocrystal floating gates is very promising because of its well-established manufacturing advantages but faces the major issue of making nanocrystals close to the channel without compromising the integrity of the gate oxide. For this purpose, very-low energy ion implantation is particularly attractive. It has been demonstrated that this technique can lead, upon proper 1 keV implantation and annealing, to the formation of 2-D arrays of Si nanocrystals located at a tunneling distance from the SiO2/Si interface. To explore the benefits of this technique for memory applications, Si-nanocrystal floating-gate MOSFETs have been fabricated and electrically characterized at room temperature. Memory devices with the following characteristics have been successfully achieved: (a) write and erase speeds close to those of conventional DRAM, (b) no degradation after 1010 write/erase cycles. The nanocrystal-based memory devices demonstrated are promising candidates for dynamic memory applications and suitable for mass fabrication, as a CMOS-fully-compatible process is used.

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